median.fit.summary

来自「用verilog编辑的中值滤波器！语言旁表有注释方便理解！」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Sun Aug 17 16:01:52 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : median
Top-level Entity Name : median
Family : Cyclone II
Device : EP2C20F484C7
Timing Models : Final
Total logic elements : 593 / 18,752 ( 3 % )
    Total combinational functions : 584 / 18,752 ( 3 % )
    Dedicated logic registers : 324 / 18,752 ( 2 % )
Total registers : 324
Total pins : 95 / 315 ( 30 % )
Total virtual pins : 0
Total memory bits : 41,472 / 239,616 ( 17 % )
Embedded Multiplier 9-bit elements : 1 / 52 ( 2 % )
Total PLLs : 0 / 4 ( 0 % )