4 位数字频率计控制模块.txt

Verilog HDL下的4 位数字频率计控制模块源代码

4 位数字频率计控制模块
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst) begin count_en=0; load=1; end
else begin
count_en=~count_en;
load=~count_en; //load 信号的产生
end
end
assign count_clr=~clk&load; //count_clr 信号的产生
endmodule