prev_cmp_1013.tan.qmsg

用verilog写的对ad0809的控制

{ "Info" "ITDB_FULL_TPD_RESULT" "EOC altera_auto_signaltap_0_EOC_ae 9.257 ns Longest " "Info: Longest tpd from source pin \"EOC\" to destination pin \"altera_auto_signaltap_0_EOC_ae\" is 9.257 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns EOC 1 PIN PIN_56 5 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; PIN Node = 'EOC'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { EOC } "NODE_NAME" } } { "ad0809.v" "" { Text "F:/72quartus/ADcontrol/ad0809.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.886 ns) + CELL(0.319 ns) 8.189 ns altera_auto_signaltap_0_EOC_signaltap_lcell 2 COMB LCCOMB_X25_Y6_N0 1 " "Info: 2: + IC(6.886 ns) + CELL(0.319 ns) = 8.189 ns; Loc. = LCCOMB_X25_Y6_N0; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_EOC_signaltap_lcell'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "7.205 ns" { EOC altera_auto_signaltap_0_EOC_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(0.000 ns) 9.257 ns altera_auto_signaltap_0_EOC_ae 3 PIN LCCOMB_X26_Y8_N0 0 " "Info: 3: + IC(1.068 ns) + CELL(0.000 ns) = 9.257 ns; Loc. = LCCOMB_X26_Y8_N0; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_EOC_ae'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.068 ns" { altera_auto_signaltap_0_EOC_signaltap_lcell altera_auto_signaltap_0_EOC_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.303 ns ( 14.08 % ) " "Info: Total cell delay = 1.303 ns ( 14.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.954 ns ( 85.92 % ) " "Info: Total interconnect delay = 7.954 ns ( 85.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "9.257 ns" { EOC altera_auto_signaltap_0_EOC_signaltap_lcell altera_auto_signaltap_0_EOC_ae } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "9.257 ns" { EOC {} EOC~combout {} altera_auto_signaltap_0_EOC_signaltap_lcell {} altera_auto_signaltap_0_EOC_ae {} } { 0.000ns 0.000ns 6.886ns 1.068ns } { 0.000ns 0.984ns 0.319ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 1.760 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.760 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.385 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.831 ns) + CELL(0.000 ns) 3.831 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 429 " "Info: 2: + IC(3.831 ns) + CELL(0.000 ns) = 3.831 ns; Loc. = CLKCTRL_G1; Fanout = 429; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.831 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 5.385 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 3 REG LCFF_X23_Y11_N19 1 " "Info: 3: + IC(0.888 ns) + CELL(0.666 ns) = 5.385 ns; Loc. = LCFF_X23_Y11_N19; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_