ad0809.tan.qmsg

用verilog写的对ad0809的控制

{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 2.466 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.466 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.398 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.831 ns) + CELL(0.000 ns) 3.831 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 660 " "Info: 2: + IC(3.831 ns) + CELL(0.000 ns) = 3.831 ns; Loc. = CLKCTRL_G0; Fanout = 660; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.831 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.901 ns) + CELL(0.666 ns) 5.398 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out 3 REG LCFF_X18_Y15_N13 2 " "Info: 3: + IC(0.901 ns) + CELL(0.666 ns) = 5.398 ns; Loc. = LCFF_X18_Y15_N13; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 739 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.34 % ) " "Info: Total cell delay = 0.666 ns ( 12.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.732 ns ( 87.66 % ) " "Info: Total interconnect delay = 4.732 ns ( 87.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "5.398 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "5.398 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out {} } { 0.000ns 3.831ns 0.901ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 739 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.238 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.238 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDIUTAP 1 PIN JTAG_X1_Y10_N0 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 11; PIN Node = 'altera_internal_jtag~TDIUTAP'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDIUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.924 ns) + CELL(0.206 ns) 3.130 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out~7 2 COMB LCCOMB_X18_Y15_N12 1 " "Info: 2: + IC(2.924 ns) + CELL(0.206 ns) = 3.130 ns; Loc. = LCCOMB_X18_Y15_N12; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out~7'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.130 ns" { altera_internal_jtag~TDIUTAP sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out~7 } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 739 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.238 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out 3 REG LCFF_X18_Y15_N13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.238 ns; Loc. = LCFF_X18_Y15_N13; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|bypass_reg_out'" {  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out~7 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out } "NODE_NAME" } } { "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/c72/quartus/libraries/megafunctions/sld_signaltap.vhd" 739 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 9.70 % ) " "Info: Total cell delay = 0.314 ns ( 9.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.924 ns ( 90.30 % ) " "Info: Total interconnect delay = 2.924 ns ( 90.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/c72/quartus/bin/TimingClosureFloorplan.fld" "" "3.238 ns" { altera_internal_jtag~TDIUTAP sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out~7 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out } "NODE_NAME" } } { "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/c72/quartus/bin/Technology_Viewer.qrui" "3.238 ns" { altera_internal_jtag~TDIUTAP {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out~7 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|bypass_reg_out {} } { 0.000ns 2.924ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %