ad0809.map.rpt

用verilog写的对ad0809的控制

Analysis & Synthesis report for ad0809
Tue Oct 14 15:26:04 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. State Machine - |ad0809|CS
  5. State Machine - |ad0809|NS
  6. State Machine - |ad0809|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state
  7. Registers Protected by Synthesis
  8. Registers Removed During Synthesis
  9. Removed Registers Triggering Further Register Optimizations
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
 12. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity
 13. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_k7p3:auto_generated
 14. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_k7p3:auto_generated|altsyncram_0hq1:altsyncram1
 15. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
 16. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
 18. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
 19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 20. Source assignments for sld_hub:sld_hub_inst
 21. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 22. Parameter Settings for User Entity Instance: Top-level Entity: |ad0809
 23. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 24. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 25. SignalTap II Logic Analyzer Settings
 26. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Oct 14 15:26:04 2008    ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                      ; ad0809                                   ;
; Top-level Entity Name              ; ad0809                                   ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 41                                       ;
;     Total combinational functions  ; 41                                       ;
;     Dedicated logic registers      ; 40                                       ;
; Total registers                    ; N/A until Partition Merge                ;
; Total pins                         ; N/A until Partition Merge                ;
; Total virtual pins                 ; N/A until Partition Merge                ;
; Total memory bits                  ; N/A until Partition Merge                ;