ad0809_new.v

用verilog写的对ad0809的控制

module   ad0809(clk,  //脉宽（至少100ns）
                      rst_n,scl,
                      EOC,  //约100us后EOC变为高电平转换结束
                      START, //启动信号，上升沿有效（至少100ns）
                      OE,   //高电平打开三态缓冲器输出转换数据
                      ALE,  //高电平有效，选择信道口
     //因为ADDB,ADDC都接地了，这里只有ADDA为变量
                      d1,d2,d3,d4,d5,d6,d7,d8,// //转换数据
                      led1,led2,led3,led4,led5,led6,led7,led8);
output START,OE,ALE,led1,led2,led3,led4,led5,led6,led7,led8,scl;
input EOC,clk,rst_n;
input d1,d2,d3,d4,d5,d6,d7,d8;
//output[7:0] DATA_R;
reg START,OE,ALE,ADDA;
reg[7:0] DATA_R;

 

reg[4:0]   CS,NS;
reg s1,s2,s3,s4,s5,s6,s7,s8,led1,led2,led3,led4,led5,led6,led7,led8;
parameter  IDLE=5'b00001,START_H=5'b00010,START_L=5'b00100,CHECK_END=5'b01000,GET_DATA=5'b10000;

reg [9:0]temp,temp1;
reg scl;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
temp<=10'd0;
scl<=1'b0;
end
else if(temp==100) begin
	temp<=1'b0;
	scl<=~scl;end
	else temp<=temp+1;

always @(posedge scl or negedge rst_n)
	if(!rst_n) begin
		START<=1'b1;
		temp1<=1'b0;end 
	else if(temp==500) begin
	   START<=~START;
	   temp1<=1'b0;end
	else temp1<=temp1+1;
	
always @(posedge scl)
case(CS)
IDLE:
      NS=START_H;
START_H:     
      NS=START_L;
START_L:
      NS=CHECK_END;
CHECK_END:
if(EOC)
      NS=GET_DATA;
else
      NS=CHECK_END;
GET_DATA:
      NS=IDLE;     
default:
      NS=IDLE;
endcase  

 
always @(posedge scl)
if(!rst_n)
      CS<=IDLE;
else 
      CS<=NS;
  

always @(posedge clk)
case(NS)
IDLE:
      begin
      OE<=0;
      START<=0;
      ALE<=0;
	  led1<=s1;
	  led2<=s2;
	  led3<=s3;
	  led4<=s4;
	  led5<=s5;
	  led6<=s6;
	  led7<=s7;
	  led8<=s8;
      end
START_H:     
      begin
      OE<=0;
      START<=1;     //产生启动信号 one state should last more than 100ns
      ALE<=1;//选择信道口IN0
      end
START_L:
      begin
      OE<=0;
      START<=0;
      ALE<=1;//启动信号脉宽要足够长,在启动的时候ALE要一直有效
      end
CHECK_END:
      begin
      OE<=0;
      START<=0;
      ALE<=0;
      end
GET_DATA:
      begin
      OE<=1;         //高电平打开三态缓冲器输出转换数据
//      DATA_R<=DATA;//提取转换数据
	  s1<=d1;
	  s2<=d2;
	  s3<=d3;
	  s4<=d4;
	  s5<=d5;
	  s6<=d6;
	  s7<=d7;
	  s8<=d8;
      START<=0;
      ALE<=0;
      end 
default:
      begin
      OE<=0;
      START<=0;
      ALE<=0;
      end
endcase         
   

endmodule