seg7led.sta.rpt

Verilog HDL源码

TimeQuest Timing Analyzer report for seg7led
Fri May 30 15:33:34 2008
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Slow 1200mV 85C Model Fmax Summary
  5. Slow 1200mV 85C Model Setup Summary
  6. Slow 1200mV 85C Model Hold Summary
  7. Slow 1200mV 85C Model Recovery Summary
  8. Slow 1200mV 85C Model Removal Summary
  9. Slow 1200mV 85C Model Minimum Pulse Width
 10. Slow 1200mV 0C Model Fmax Summary
 11. Slow 1200mV 0C Model Setup Summary
 12. Slow 1200mV 0C Model Hold Summary
 13. Slow 1200mV 0C Model Recovery Summary
 14. Slow 1200mV 0C Model Removal Summary
 15. Slow 1200mV 0C Model Minimum Pulse Width
 16. Fast 1200mV 0C Model Setup Summary
 17. Fast 1200mV 0C Model Hold Summary
 18. Fast 1200mV 0C Model Recovery Summary
 19. Fast 1200mV 0C Model Removal Summary
 20. Fast 1200mV 0C Model Minimum Pulse Width
 21. Board Trace Model Assignments
 22. Slow Corner Signal Integrity Metrics
 23. Fast Corner Signal Integrity Metrics
 24. Setup Transfers
 25. Hold Transfers
 26. Report TCCS
 27. Report RSKM
 28. Unconstrained Paths
 29. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version ;
; Revision Name      ; seg7led                                                         ;
; Device Family      ; Cyclone III                                                     ;
; Device Name        ; EP3C25Q240C8                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Enabled                                                         ;
+--------------------+-----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                       ;
+-----------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------+
; Clock Name            ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                   ;
+-----------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------+
; clk                   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk }                   ;
; int_div:inst6|div_out ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { int_div:inst6|div_out } ;
+-----------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------+


+--------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                       ;
+------------+-----------------+-----------------------+-------------------+
; Fmax       ; Restricted Fmax ; Clock Name            ; Note              ;
+------------+-----------------+-----------------------+-------------------+
; 229.36 MHz ; 229.36 MHz      ; clk                   ;                   ;
; 350.14 MHz ; 350.02 MHz      ; int_div:inst6|div_out ; limit due to tmin ;
+------------+-----------------+-----------------------+-------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary            ;
+-----------------------+--------+---------------+
; Clock                 ; Slack  ; End Point TNS ;
+-----------------------+--------+---------------+
; clk                   ; -3.360 ; -124.159      ;
; int_div:inst6|div_out ; -1.856 ; -20.727       ;