📄 clock.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A3 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A4 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A5 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A6 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 14/22( 63%)
A7 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 10/22( 45%)
A9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A10 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
A11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
A12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 13/22( 59%)
A13 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
A14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 15/22( 68%)
A16 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 10/22( 45%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 18/22( 81%)
A19 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
A20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 11/22( 50%)
A21 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 1/2 0/2 8/22( 36%)
A22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 15/22( 68%)
A23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
A24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
B14 8/ 8(100%) 6/ 8( 75%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
D5 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 2/22( 9%)
D7 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
D11 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F16 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
F17 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
F18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 10/22( 45%)
F19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
F20 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
F21 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
F22 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
F23 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
F24 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 19/96 ( 19%)
Total logic cells used: 273/1152 ( 23%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.40/4 ( 85%)
Total fan-in: 929/4608 ( 20%)
Total input pins required: 8
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 273
Total flipflops required: 87
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 71/1152 ( 6%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 1 8 8 8 8 8 8 8 8 8 8 8 0 8 8 8 8 1 8 8 8 8 8 8 8 178/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 1 0 0 0 0 0 0 0 0 9/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 5 0 4 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 7 8 8 8 8 8 7 7 8 70/0
Total: 1 8 8 8 13 8 12 8 8 8 15 8 0 9 16 8 16 9 16 16 16 16 15 15 16 273/0
Device-Specific Information: f:\clock\clock.rpt
clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
124 - - - -- INPUT 0 0 0 8 A1
56 - - - -- INPUT 0 0 0 7 B1
126 - - - -- INPUT 0 0 0 7 change
55 - - - -- INPUT G 0 0 0 0 clk
125 - - - -- INPUT G 0 0 0 0 clk_lk
54 - - - -- INPUT 0 0 0 56 reset
101 - - A -- INPUT 0 0 0 2 reset1
102 - - A -- INPUT 0 0 0 6 turn
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\clock\clock.rpt
clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - F -- OUTPUT 0 1 0 0 a
81 - - F -- OUTPUT 0 1 0 0 b
30 - - F -- OUTPUT 0 1 0 0 c
33 - - F -- OUTPUT 0 1 0 0 d
32 - - F -- OUTPUT 0 1 0 0 e
31 - - F -- OUTPUT 0 1 0 0 f
79 - - F -- OUTPUT 0 1 0 0 g
144 - - A -- OUTPUT 0 1 0 0 Ld_alert
7 - - A -- OUTPUT 0 1 0 0 Ld_h
8 - - A -- OUTPUT 0 1 0 0 Ld_m
14 - - C -- OUTPUT 0 1 0 0 Ms1
100 - - A -- OUTPUT 0 1 0 0 Ms2
49 - - - 14 OUTPUT 0 1 0 0 Ms3
122 - - - 13 OUTPUT 0 1 0 0 Ms4
128 - - - 13 OUTPUT 0 1 0 0 Ms5
51 - - - 14 OUTPUT 0 1 0 0 Ms6
143 - - A -- OUTPUT 0 1 0 0 out
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\clock\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - F 23 AND2 0 3 0 3 |lpm_add_sub:2022|addcore:adder|:63
- 7 - A 03 AND2 0 2 0 1 |lpm_add_sub:2023|addcore:adder|:55
- 5 - A 03 AND2 0 3 0 1 |lpm_add_sub:2023|addcore:adder|:59
- 2 - A 07 OR2 ! 0 2 0 2 |lpm_add_sub:2025|addcore:adder|:55
- 3 - A 05 AND2 0 2 0 3 |lpm_add_sub:2026|addcore:adder|:55
- 5 - A 12 OR2 0 3 0 2 |lpm_add_sub:2026|addcore:adder|:69
- 1 - D 07 AND2 0 3 0 3 |lpm_add_sub:2027|addcore:adder|:125
- 4 - D 11 AND2 0 3 0 4 |lpm_add_sub:2027|addcore:adder|:133
- 7 - F 17 AND2 0 2 0 1 |lpm_add_sub:2030|addcore:adder|:55
- 5 - F 19 OR2 ! 0 2 0 3 |lpm_add_sub:2031|addcore:adder|:55
- 2 - F 24 OR2 0 4 0 2 |lpm_add_sub:2031|addcore:adder|:69
- 6 - A 14 AND2 0 2 0 1 |lpm_add_sub:2034|addcore:adder|:55
- 4 - A 14 AND2 0 3 0 1 |lpm_add_sub:2034|addcore:adder|:59
- 4 - A 23 AND2 0 2 0 3 |lpm_add_sub:2035|addcore:adder|:55
- 5 - A 08 AND2 0 2 0 1 |lpm_add_sub:2036|addcore:adder|:55
- 6 - A 02 AND2 0 3 0 1 |lpm_add_sub:2036|addcore:adder|:59
- 1 - A 09 AND2 0 2 0 2 |lpm_add_sub:2037|addcore:adder|:55
- 7 - B 14 DFFE + 0 2 0 6 counter2 (:70)
- 4 - B 14 DFFE + 0 1 0 7 counter1 (:71)
- 1 - B 16 DFFE + 0 0 0 8 counter0 (:72)
- 8 - B 14 AND2 0 3 1 4 :73
- 6 - B 14 AND2 0 3 1 4 :84
- 1 - B 14 AND2 0 3 1 4 :95
- 2 - B 14 AND2 0 3 1 4 :106
- 3 - B 14 AND2 0 3 1 4 :117
- 5 - B 14 AND2 0 3 1 4 :128
- 7 - F 23 DFFE + 0 2 0 1 m4 (:218)
- 6 - F 23 DFFE + 0 1 0 2 m3 (:219)
- 4 - F 23 DFFE + 0 2 0 1 m2 (:220)
- 2 - F 23 DFFE + 0 1 0 2 m1 (:221)
- 3 - F 23 DFFE + 0 0 0 3 m0 (:222)
- 1 - F 23 DFFE + 0 3 0 12 flag (:234)
- 1 - A 04 AND2 s ! 0 2 0 2 ~238~1
- 2 - A 04 AND2 0 4 0 2 :238
- 8 - F 20 AND2 0 4 0 7 :256
- 5 - F 20 AND2 0 3 0 2 :282
- 1 - F 20 OR2 0 4 0 1 :318
- 4 - F 20 OR2 0 4 0 1 :319
- 3 - F 22 OR2 0 3 0 1 :320
- 5 - A 04 AND2 s 0 2 0 4 ~354~1
- 6 - A 03 OR2 0 4 0 1 :354
- 8 - A 03 OR2 0 4 0 1 :355
- 4 - A 04 OR2 0 4 0 1 :356
- 4 - A 03 OR2 0 3 0 1 :357
- 8 - A 04 AND2 s 0 2 0 3 ~358~1
- 3 - F 20 AND2 0 3 0 1 :358
- 6 - F 20 AND2 0 2 0 1 :359
- 4 - F 22 AND2 0 2 0 1 :360
- 2 - A 21 OR2 s 3 0 0 8 ~402~1
- 5 - F 22 OR2 s 0 4 0 1 ~402~2
- 1 - A 03 DFFE + 0 3 0 3 sec17 (:411)
- 2 - A 03 DFFE + 0 3 0 5 sec16 (:412)
- 7 - A 04 DFFE + 0 3 0 5 sec15 (:413)
- 3 - A 03 DFFE + 0 3 0 7 sec14 (:414)
- 7 - F 20 DFFE + 0 3 0 7 sec13 (:415)
- 2 - F 20 DFFE + 0 3 0 5 sec12 (:416)
- 1 - F 22 DFFE + 0 3 0 6 sec11 (:417)
- 8 - F 22 DFFE + 0 3 0 7 sec10 (:418)
- 3 - A 04 AND2 0 2 0 10 :431
- 1 - A 05 AND2 0 4 0 9 :432
- 8 - A 07 AND2 0 4 0 2 :438
- 7 - A 07 AND2 s 0 2 0 4 ~468~1
- 4 - A 11 AND2 0 3 0 1 :497
- 7 - A 12 OR2 0 4 0 1 :498
- 8 - A 05 OR2 0 4 0 1 :499
- 4 - A 10 DFFE + 4 0 0 1 tmin (:540)
- 7 - D 11 DFFE + 0 3 0 1 s7 (:550)
- 6 - D 11 DFFE + 0 2 0 2 s6 (:551)
- 5 - D 11 DFFE + 0 1 0 3 s5 (:552)
- 3 - D 11 DFFE + 0 2 0 1 s4 (:553)
- 2 - D 11 DFFE + 0 1 0 2 s3 (:554)
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