📄 clo.rpt
字号:
- 6 - D 05 OR2 0 3 0 1 |clock:1|:1559
- 6 - D 09 OR2 0 3 0 1 |clock:1|:1560
- 6 - D 11 OR2 0 3 0 1 |clock:1|:1561
- 7 - D 01 OR2 0 3 0 1 |clock:1|:1566
- 7 - D 05 OR2 0 3 0 1 |clock:1|:1567
- 7 - D 09 OR2 0 3 0 1 |clock:1|:1568
- 7 - D 11 OR2 0 3 0 1 |clock:1|:1569
- 8 - D 01 OR2 0 3 0 1 |clock:1|:1574
- 8 - D 05 OR2 0 3 0 1 |clock:1|:1575
- 8 - D 09 OR2 0 3 0 1 |clock:1|:1576
- 8 - D 11 OR2 0 3 0 1 |clock:1|:1577
- 1 - D 01 OR2 0 3 0 8 |clock:1|:1582
- 2 - D 05 OR2 0 3 0 8 |clock:1|:1583
- 2 - D 09 OR2 0 3 0 8 |clock:1|:1584
- 1 - D 11 OR2 0 3 0 8 |clock:1|:1585
- 1 - B 14 OR2 0 4 1 0 |clock:1|:1723
- 3 - B 17 OR2 s 0 4 0 1 |clock:1|~1724~1
- 2 - B 14 OR2 0 2 1 0 |clock:1|:1724
- 1 - B 17 OR2 s 0 4 0 2 |clock:1|~1725~1
- 1 - B 15 OR2 0 2 1 0 |clock:1|:1725
- 4 - B 17 OR2 s 0 4 0 1 |clock:1|~1726~1
- 2 - B 16 OR2 0 2 1 0 |clock:1|:1726
- 5 - B 17 OR2 0 4 1 1 |clock:1|:1727
- 2 - B 17 OR2 0 4 1 1 |clock:1|:1728
- 6 - B 17 OR2 0 4 1 0 |clock:1|:1729
- 3 - D 03 DFFE 5 0 1 0 |clock:1|:1754
- 2 - D 03 DFFE 5 0 1 0 |clock:1|:1772
- 3 - D 14 DFFE 2 1 1 0 |clock:1|:1797
- 2 - E 21 OR2 s 0 4 0 1 |clock:1|~1835~1
- 2 - D 14 OR2 s 0 4 0 1 |clock:1|~1835~2
- 8 - D 21 OR2 s 0 4 0 1 |clock:1|~1835~3
- 5 - E 20 OR2 s 0 4 0 1 |clock:1|~1835~4
- 4 - D 14 AND2 s 0 4 0 2 |clock:1|~1835~5
- 4 - D 17 OR2 s 0 4 0 1 |clock:1|~1835~6
- 3 - E 01 OR2 s 0 4 0 1 |clock:1|~1835~7
- 4 - E 18 OR2 s 0 4 0 1 |clock:1|~1835~8
- 3 - E 08 OR2 s 0 4 0 1 |clock:1|~1835~9
- 2 - D 17 AND2 s 0 4 0 2 |clock:1|~1835~10
- 2 - E 24 OR2 s 0 4 0 2 |clock:1|~1837~1
- 4 - E 24 OR2 s 0 3 0 1 |clock:1|~1837~2
- 5 - E 24 OR2 s 0 4 0 1 |clock:1|~1837~3
- 6 - E 24 OR2 s 0 2 0 1 |clock:1|~1837~4
- 7 - E 24 OR2 s 0 4 0 1 |clock:1|~1837~5
- 1 - E 24 OR2 0 4 0 3 |clock:1|:1837
- 6 - D 14 AND2 0 4 0 1 |clock:1|:1887
- 5 - D 14 OR2 0 4 0 1 |clock:1|:1889
- 7 - D 14 DFFE 3 2 0 2 |clock:1|out1 (|clock:1|:1895)
- 8 - D 03 AND2 s 2 2 0 2 |clock:1|~1932~1
- 6 - D 17 AND2 s 0 4 0 1 |clock:1|~1932~2
- 8 - D 19 AND2 s 1 3 0 1 |clock:1|~1932~3
- 1 - D 19 AND2 s 0 4 0 1 |clock:1|~1932~4
- 8 - D 14 DFFE 1 4 0 1 |clock:1|out2 (|clock:1|:1934)
- 1 - D 14 OR2 0 2 1 0 |clock:1|:1935
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: g:\clock\clo.rpt
clo
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 4/ 96( 4%) 2/ 48( 4%) 5/ 48( 10%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 47/ 96( 48%) 27/ 48( 56%) 27/ 48( 56%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
E: 34/ 96( 35%) 16/ 48( 33%) 20/ 48( 41%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
F: 4/ 96( 4%) 1/ 48( 2%) 0/ 48( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 6/24( 25%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: g:\clock\clo.rpt
clo
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 41 clk
INPUT 30 clk_lk
LCELL 8 |clock:1|:1024
LCELL 8 |clock:1|:1289
Device-Specific Information: g:\clock\clo.rpt
clo
** EQUATIONS **
a1 : INPUT;
b1 : INPUT;
change : INPUT;
clk : INPUT;
clk_lk : INPUT;
reset : INPUT;
reset1 : INPUT;
turn : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC1_B14;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC2_B14;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC1_B15;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC2_B16;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC5_B17;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC2_B17;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC6_B17;
-- Node name is 'ld_alter'
-- Equation name is 'ld_alter', type is output
ld_alter = _LC3_D14;
-- Node name is 'ld_h'
-- Equation name is 'ld_h', type is output
ld_h = _LC3_D3;
-- Node name is 'ld_m'
-- Equation name is 'ld_m', type is output
ld_m = _LC2_D3;
-- Node name is 'ms1'
-- Equation name is 'ms1', type is output
ms1 = _LC8_F11;
-- Node name is 'ms2'
-- Equation name is 'ms2', type is output
ms2 = _LC3_F11;
-- Node name is 'ms3'
-- Equation name is 'ms3', type is output
ms3 = _LC4_F11;
-- Node name is 'ms4'
-- Equation name is 'ms4', type is output
ms4 = _LC6_F11;
-- Node name is 'ms5'
-- Equation name is 'ms5', type is output
ms5 = _LC1_F11;
-- Node name is 'ms6'
-- Equation name is 'ms6', type is output
ms6 = _LC2_F11;
-- Node name is 'out'
-- Equation name is 'out', type is output
out = _LC1_D14;
-- Node name is '|clock:1|:72' = '|clock:1|counter0'
-- Equation name is '_LC1_F12', type is buried
_LC1_F12 = DFFE(!_LC1_F12, clk_lk, VCC, VCC, VCC);
-- Node name is '|clock:1|:71' = '|clock:1|counter1'
-- Equation name is '_LC5_F11', type is buried
_LC5_F11 = DFFE( _EQ001, clk_lk, VCC, VCC, VCC);
_EQ001 = _LC1_F12 & !_LC5_F11
# !_LC1_F12 & _LC5_F11;
-- Node name is '|clock:1|:70' = '|clock:1|counter2'
-- Equation name is '_LC7_F11', type is buried
_LC7_F11 = DFFE( _EQ002, clk_lk, VCC, VCC, VCC);
_EQ002 = !_LC1_F12 & _LC7_F11
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