📄 clo.rpt
字号:
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
out | 17 92 | RESERVED
ld_m | 18 91 | RESERVED
ld_h | 19 EPF10K20TC144-3 90 | RESERVED
ld_alter | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | b1
RESERVED | 23 86 | a1
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | change
RESERVED | 27 82 | reset
RESERVED | 28 81 | reset1
RESERVED | 29 80 | turn
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R g f V e d c b G a V V G G G G G R R V R R R R G R R R R V R
E E E N E E C N C C N N N N N E E C E E E E N E E E E C E
S S S D S S C D C C D D D D D S S C S S S S D S S S S C S
E E E I E E I I I I I I I I I E E I E E E E I E E E E I E
R R R O R R O O N N N N N N N R R O R R R R O R R R R O R
V V V V V T T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: g:\clock\clo.rpt
clo
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/22( 27%)
B15 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B17 6/ 8( 75%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 4/22( 18%)
D1 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 17/22( 77%)
D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
D3 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 1/2 0/2 10/22( 45%)
D4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
D5 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 17/22( 77%)
D6 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 5/22( 22%)
D7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
D8 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D9 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 17/22( 77%)
D10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
D11 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 17/22( 77%)
D12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
D13 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
D14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 16/22( 72%)
D15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
D17 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 15/22( 68%)
D18 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D19 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 11/22( 50%)
D20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 12/22( 54%)
D21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
D24 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E1 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 2/2 0/2 12/22( 54%)
E3 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
E4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E5 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 17/22( 77%)
E6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E7 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 0/2 11/22( 50%)
E8 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 13/22( 59%)
E10 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
E11 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
E12 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 11/22( 50%)
E13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 5/22( 22%)
E14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E16 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
E17 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
E18 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 13/22( 59%)
E19 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
E20 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 2/2 0/2 10/22( 45%)
E21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
E23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
E24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 18/22( 81%)
F11 8/ 8(100%) 8/ 8(100%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
F12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 25/96 ( 26%)
Total logic cells used: 269/1152 ( 23%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.38/4 ( 84%)
Total fan-in: 911/4608 ( 19%)
Total input pins required: 8
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 269
Total flipflops required: 87
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 68/1152 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 6 0 0 0 0 0 0 0 10/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 8 1 8 8 8 8 8 7 8 8 8 1 0 2 8 8 0 6 7 8 8 1 0 0 8 137/0
E: 8 0 8 8 8 1 8 8 0 2 2 8 0 8 1 0 8 8 8 1 8 1 0 1 8 113/0
F: 0 0 0 0 0 0 0 0 0 0 8 1 0 0 0 0 0 0 0 0 0 0 0 0 0 9/0
Total: 16 1 16 16 16 9 16 15 8 10 18 10 0 10 11 9 9 20 15 9 16 2 0 1 16 269/0
Device-Specific Information: g:\clock\clo.rpt
clo
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - E -- INPUT 0 0 0 8 a1
87 - - E -- INPUT 0 0 0 7 b1
83 - - E -- INPUT 0 0 0 7 change
122 - - - 13 INPUT 0 0 0 41 clk
128 - - - 13 INPUT 0 0 0 30 clk_lk
82 - - E -- INPUT 0 0 0 56 reset
81 - - F -- INPUT 0 0 0 2 reset1
80 - - F -- INPUT 0 0 0 6 turn
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\clock\clo.rpt
clo
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
51 - - - 14 OUTPUT 0 1 0 0 a
49 - - - 14 OUTPUT 0 1 0 0 b
48 - - - 15 OUTPUT 0 1 0 0 c
47 - - - 16 OUTPUT 0 1 0 0 d
46 - - - 17 OUTPUT 0 1 0 0 e
44 - - - 18 OUTPUT 0 1 0 0 f
43 - - - 18 OUTPUT 0 1 0 0 g
20 - - D -- OUTPUT 0 1 0 0 ld_alter
19 - - D -- OUTPUT 0 1 0 0 ld_h
18 - - D -- OUTPUT 0 1 0 0 ld_m
8 - - A -- OUTPUT 0 1 0 0 ms1
102 - - A -- OUTPUT 0 1 0 0 ms2
101 - - A -- OUTPUT 0 1 0 0 ms3
100 - - A -- OUTPUT 0 1 0 0 ms4
99 - - B -- OUTPUT 0 1 0 0 ms5
98 - - B -- OUTPUT 0 1 0 0 ms6
17 - - D -- OUTPUT 0 1 0 0 out
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: g:\clock\clo.rpt
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