fenpin.vhd

此程序是用硬件描述语言VHDL编写的分频程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fenpin is
port ( clk   : in std_logic;
       clkout: out std_logic);
end fenpin;

architecture behavioral of fenpin is
signal tmp: std_logic := '0';
begin
    process (clk)
    begin
        if (clk'event and clk = '1') then 
           tmp <= not tmp;
        end if;
    end process;
    clkout <= tmp;
end behavioral;