dff.vhd

来自「此程序是用硬件描述语言VHDL编写的分频程序」· VHDL 代码 · 共 21 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
port (d: in std_logic;
      clk: in std_logic;
	 q: out std_logic); 
end dff;

architecture Behavioral of dff is
begin
	process(clk)
	begin
	     if clk'event and clk = '1' then 
		     q <= d;
		end if;
	end process;
end Behavioral;