compare.vhd

来自「此程序是用硬件描述语言VHDL编写的分频程序」· VHDL 代码 · 共 39 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bijiao is
port ( data1, data2: in std_logic;
       clk: in std_logic;
	  sting: out std_logic);
end bijiao;

architecture behave of bijiao is
signal q: std_logic;
begin
     process (clk)
	variable cnt: integer range 0 to 4;
	begin
	     if clk'event and clk = '1' then
		    if cnt < 4 then
		         cnt := cnt + 1;
			    q <= '0';
		    else
		         q <= '1';
		    end if;
		end if;
	end process;

	process (clk, q, data1, data2)
	begin
	     if clk'event and clk = '0' and q = '1' then
		    if data1 = data2 then
			    sting <= '0';
		    else
		         sting <= '1';
		    end if;
		end if;
	end process;
end behave;