📄 jianfaqi.tan.rpt
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Timing Analyzer report for jianfaqi
Sat Oct 21 15:59:56 2006
Version 6.0 Build 178 04/27/2006 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.345 ns ; B[0] ; s[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 13.345 ns ; B[0] ; s[3] ;
; N/A ; None ; 12.866 ns ; B[0] ; j[4] ;
; N/A ; None ; 12.653 ns ; A[0] ; s[3] ;
; N/A ; None ; 12.429 ns ; B[3] ; s[3] ;
; N/A ; None ; 12.291 ns ; B[0] ; s[2] ;
; N/A ; None ; 12.174 ns ; A[0] ; j[4] ;
; N/A ; None ; 11.983 ns ; B[0] ; j[3] ;
; N/A ; None ; 11.952 ns ; B[3] ; j[4] ;
; N/A ; None ; 11.758 ns ; B[0] ; s[1] ;
; N/A ; None ; 11.687 ns ; B[2] ; s[3] ;
; N/A ; None ; 11.599 ns ; A[0] ; s[2] ;
; N/A ; None ; 11.291 ns ; A[0] ; j[3] ;
; N/A ; None ; 11.266 ns ; B[0] ; j[2] ;
; N/A ; None ; 11.208 ns ; B[2] ; j[4] ;
; N/A ; None ; 11.069 ns ; A[0] ; j[1] ;
; N/A ; None ; 11.069 ns ; A[0] ; s[1] ;
; N/A ; None ; 10.976 ns ; A[2] ; s[3] ;
; N/A ; None ; 10.786 ns ; B[0] ; j[1] ;
; N/A ; None ; 10.745 ns ; A[3] ; s[3] ;
; N/A ; None ; 10.687 ns ; A[0] ; s[0] ;
; N/A ; None ; 10.635 ns ; B[2] ; s[2] ;
; N/A ; None ; 10.574 ns ; A[0] ; j[2] ;
; N/A ; None ; 10.497 ns ; A[2] ; j[4] ;
; N/A ; None ; 10.403 ns ; B[0] ; s[0] ;
; N/A ; None ; 10.325 ns ; B[2] ; j[3] ;
; N/A ; None ; 10.265 ns ; A[3] ; j[4] ;
; N/A ; None ; 9.923 ns ; A[2] ; s[2] ;
; N/A ; None ; 9.826 ns ; B[1] ; s[3] ;
; N/A ; None ; 9.616 ns ; A[1] ; s[3] ;
; N/A ; None ; 9.614 ns ; A[2] ; j[3] ;
; N/A ; None ; 9.347 ns ; B[1] ; j[4] ;
; N/A ; None ; 9.137 ns ; A[1] ; j[4] ;
; N/A ; None ; 8.772 ns ; B[1] ; s[2] ;
; N/A ; None ; 8.562 ns ; A[1] ; s[2] ;
; N/A ; None ; 8.464 ns ; B[1] ; j[3] ;
; N/A ; None ; 8.254 ns ; A[1] ; j[3] ;
; N/A ; None ; 8.239 ns ; B[1] ; s[1] ;
; N/A ; None ; 8.029 ns ; A[1] ; s[1] ;
; N/A ; None ; 7.747 ns ; B[1] ; j[2] ;
; N/A ; None ; 7.537 ns ; A[1] ; j[2] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
Info: Processing started: Sat Oct 21 15:59:55 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jianfaqi -c jianfaqi --timing_analysis_only
Info: Longest tpd from source pin "B[0]" to destination pin "s[3]" is 13.345 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 4; PIN Node = 'B[0]'
Info: 2: + IC(5.613 ns) + CELL(0.590 ns) = 7.672 ns; Loc. = LC_X1_Y11_N5; Fanout = 3; COMB Node = 'fullsubstractor:u1|borrow~103'
Info: 3: + IC(0.416 ns) + CELL(0.442 ns) = 8.530 ns; Loc. = LC_X1_Y11_N2; Fanout = 3; COMB Node = 'fullsubstractor:u2|borrow~132'
Info: 4: + IC(0.449 ns) + CELL(0.292 ns) = 9.271 ns; Loc. = LC_X1_Y11_N3; Fanout = 1; COMB Node = 'fullsubstractor:u3|difference'
Info: 5: + IC(1.966 ns) + CELL(2.108 ns) = 13.345 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 's[3]'
Info: Total cell delay = 4.901 ns ( 36.73 % )
Info: Total interconnect delay = 8.444 ns ( 63.27 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Oct 21 15:59:56 2006
Info: Elapsed time: 00:00:02
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