regkeys

XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创

CommandLine
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\cpldfit.exe -ise F:/MiniStep_v1.0/MiniStep.ise -intstyle ise -p xc9536-10-VQ44 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 36 -pterms 25 -power std -localfbk -pinfbk MiniStep.ngd
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FormatString
cpldfit <design[.ngd]> [-p <part>] [-intstyle ise|xflow|silent] [-optimize density|speed] [-nomlopt] [-ignoretspec] [-init low|high|fpga] [-slew fast|slow|auto] [-loc on|off|try] [-log <logfile>] [-wysiwyg] [-keepio] [-unused float|ground] [-power std|low|auto] [-nogclkopt] [-nogsropt] [-nogtsopt] [-ofmt abel|vhdl|verilog] [-exhaust] [-pterms <limit:1,90>] [-inputs <limit:2,36>] [-nouim] [-localfbk] [-pinfbk] [--blkfanin <limit:30,36>] [--nomdf] [--noxml] [--neweqn] [--noibis] [--htmlrpt] [--libxslt <limit:-1,10>] [--noselfpinlock] [--readngd_debug] [--write_mapped_network <limit:1,2>] [--write_optimized_network <limit:1,2>] [--fmp_debug] [--xstrategy inputs|pterms] [--xinputs <limit:-10,10>] [--xpterms <limit:-10,10>] [--readngd] [--partgen] 
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