xst.xmsgs

来自「XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创」· XMSGS 代码 · 共 20 行

<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="warning" file="Xst" num="905" delta="unknown" >&quot;<arg fmt="%s" index="1">MiniStep.v</arg>&quot; line <arg fmt="%d" index="2">157</arg>: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;reg_DlyCnt&gt;</arg>
</msg>

<msg type="warning" file="Xst" num="2474" delta="unknown" >Clock and clock enable of register &lt;<arg fmt="%s" index="1">q_reg</arg>&gt; are driven by the same logic. The clock enable is removed.
</msg>

<msg type="warning" file="Xst" num="737" delta="unknown" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">reg_DrvOut</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>

</messages>