cpldfit.xmsgs

来自「XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创」· XMSGS 代码 · 共 13 行

<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="info" file="Cpld" num="0" delta="unknown" >Inferring BUFG constraint for signal &apos;<arg fmt="%s" index="1">CHOP_CLK</arg>&apos; based upon the LOC constraint &apos;<arg fmt="%s" index="2">P43</arg>&apos;. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.
</msg>

</messages>