dispselect.map.summary

来自「verilog写的数字频率计的选择模块,用与显示的选择」· SUMMARY 代码 · 共 9 行

Flow Status : Successful - Mon Jul 17 22:44:08 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : dispselect
Top-level Entity Name : dispselect
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9
Total pins : 10