dispselect.fit.summary

来自「verilog写的数字频率计的选择模块,用与显示的选择」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Mon Jul 17 22:44:11 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : dispselect
Top-level Entity Name : dispselect
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9 / 32 ( 28 % )
Total pins : 14 / 36 ( 38 % )
Device : EPM7032SLC44-5
Timing Models : Final