dispselect.tan.summary

来自「verilog写的数字频率计的选择模块,用与显示的选择」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.800 ns
From           : disp_select[0]~reg0
To             : disp_select[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 175.44 MHz ( period = 5.700 ns )
From           : disp_select[2]~reg0
To             : disp_select[0]~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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