gate_control.hier_info

verilog写的数字频率计的控制模块,对程序进行控制

|gate_control
SW0 => always0~0.IN0
SW1 => comb~0.IN0
SW1 => fref~0.OUTPUTSELECT
SW1 => dp_s10hz~0.DATAA
SW1 => always0~0.IN1
SW2 => comb~3.IN0
SW2 => fref~1.OUTPUTSELECT
SW2 => dp_s1hz~0.OUTPUTSELECT
SW2 => dp_s10hz~0.OUTPUTSELECT
SW2 => dp_s100hz$latch$d_or.IN1
SW2 => always0~1.IN0
SW2 => dp_s100hz$latch$s_buf.IN0
f1hz => fref~0.DATAA
f10hz => fref~0.DATAB
f100hz => fref~1.DATAB
Latch_EN <= Latch_EN~1.DB_MAX_OUTPUT_PORT_TYPE
Counter_Clr <= Counter_Clr~3.DB_MAX_OUTPUT_PORT_TYPE
Counter_EN <= wire_1.DB_MAX_OUTPUT_PORT_TYPE
dp_s1hz <= dp_s1hz$latch.DB_MAX_OUTPUT_PORT_TYPE
dp_s10hz <= dp_s10hz$latch.DB_MAX_OUTPUT_PORT_TYPE
dp_s100hz <= dp_s100hz$latch.DB_MAX_OUTPUT_PORT_TYPE