gate_control.tan.rpt

verilog写的数字频率计的控制模块,对程序进行控制

                Info: Loc. = LC4; Node "fref~106"
            Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 14.700 ns ( 83.05 % )
            Info: Total interconnect delay = 3.000 ns ( 16.95 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "f10hz" has Internal fmax of 87.72 MHz between source register "wire_1" and destination register "wire_2" (period= 11.4 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "f10hz" to destination register is 17.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 1; CLK Node = 'f10hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
            Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
            Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
            Info: Total cell delay = 14.700 ns ( 83.05 % )
            Info: Total interconnect delay = 3.000 ns ( 16.95 % )
        Info: - Longest clock path from clock "f10hz" to source register is 17.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 1; CLK Node = 'f10hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
            Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
            Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 14.700 ns ( 83.05 % )
            Info: Total interconnect delay = 3.000 ns ( 16.95 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "f1hz" has Internal fmax of 87.72 MHz between source register "wire_1" and destination register "wire_2" (period= 11.4 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "f1hz" to destination register is 17.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f1hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
            Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
            Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
            Info: Total cell delay = 14.700 ns ( 83.05 % )
            Info: Total interconnect delay = 3.000 ns ( 16.95 % )
        Info: - Longest clock path from clock "f1hz" to source register is 17.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f1hz'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
            Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
            Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 14.700 ns ( 83.05 % )
            Info: Total interconnect delay = 3.000 ns ( 16.95 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "SW0" has Internal fmax of 56.82 MHz between source register "wire_1" and destination register "wire_2" (period= 17.6 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is -3.100 ns
        Info: + Shortest clock path from clock "SW0" to destination register is 8.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 9; CLK Node = 'SW0'
            Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
            Info: Total cell delay = 7.500 ns ( 88.24 % )
            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
        Info: - Longest clock path from clock "SW0" to source register is 11.600 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 9; CLK Node = 'SW0'
            Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.300 ns; Loc. = SEXP1; Fanout = 8; COMB Node = 'always0~10sexp'
            Info: 3: + IC(0.000 ns) + CELL(3.600 ns) = 7.900 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 11.600 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 9.600 ns ( 82.76 % )
            Info: Total interconnect delay = 2.000 ns ( 17.24 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "SW2" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "wire_1" and destination pin or register "wire_1" for clock "SW2" (Hold time is 1.4 ns)
    Info: + Largest clock skew is 4.600 ns
        Info: + Longest clock path from clock "SW2" to destination register is 13.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
            Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 11.100 ns ( 84.73 % )
            Info: Total interconnect delay = 2.000 ns ( 15.27 % )
        Info: - Shortest clock path from clock "SW2" to source register is 8.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 7.500 ns ( 88.24 % )
            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
    Info: - Micro clock to output delay of source is 1.300 ns
    Info: - Shortest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "SW1" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "wire_1" and destination pin or register "wire_1" for clock "SW1" (Hold time is 6.0 ns)
    Info: + Largest clock skew is 9.200 ns
        Info: + Longest clock path from clock "SW1" to destination register is 17.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'
            Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
            Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
            Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 14.700 ns ( 83.05 % )
            Info: Total interconnect delay = 3.000 ns ( 16.95 % )
        Info: - Shortest clock path from clock "SW1" to source register is 8.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
                Info: Loc. = LC4; Node "fref~106"
            Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
            Info: Total cell delay = 7.500 ns ( 88.24 % )
            Info: Total interconnect delay = 1.000 ns ( 11.76 % )
    Info: - Micro clock to output delay of source is 1.300 ns
    Info: - Shortest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: Total cell delay = 3.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
Info: tco from clock "f1hz" to destination pin "Latch_EN" through register "wire_1" is 23.800 ns
    Info: + Longest clock path from clock "f1hz" to source register is 17.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f1hz'
        Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
        Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
        Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
            Info: Loc. = LC4; Node "fref~106"
        Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: Total cell delay = 14.700 ns ( 83.05 % )
        Info: Total interconnect delay = 3.000 ns ( 16.95 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 4.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
        Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.600 ns; Loc. = LC7; Fanout = 1; COMB Node = 'Latch_EN~11'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Latch_EN'
        Info: Total cell delay = 3.800 ns ( 79.17 % )
        Info: Total interconnect delay = 1.000 ns ( 20.83 % )
Info: Longest tpd from source pin "SW2" to destination pin "dp_s100hz" is 8.100 ns
    Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'
    Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.300 ns; Loc. = SEXP1; Fanout = 8; COMB Node = 'always0~10sexp'
    Info: 3: + IC(0.000 ns) + CELL(3.600 ns) = 7.900 ns; Loc. = LC3; Fanout = 3; COMB LOOP Node = 'dp_s100hz$latch~10'
        Info: Loc. = LC3; Node "dp_s100hz$latch~10"
    Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 8.100 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'dp_s100hz'
    Info: Total cell delay = 7.100 ns ( 87.65 % )
    Info: Total interconnect delay = 1.000 ns ( 12.35 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Processing ended: Mon Jul 17 20:29:32 2006
    Info: Elapsed time: 00:00:06