📄 gate_control.tan.rpt
字号:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'SW2' ;
+------------------------------------------+--------+--------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+--------+--------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; wire_1 ; wire_1 ; SW2 ; SW2 ; None ; None ; 3.600 ns ;
; Not operational: Clock Skew > Data Delay ; wire_1 ; wire_2 ; SW2 ; SW2 ; None ; None ; 3.600 ns ;
+------------------------------------------+--------+--------+------------+----------+----------------------------+----------------------------+--------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'SW1' ;
+------------------------------------------+--------+--------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+--------+--------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; wire_1 ; wire_1 ; SW1 ; SW1 ; None ; None ; 3.600 ns ;
; Not operational: Clock Skew > Data Delay ; wire_1 ; wire_2 ; SW1 ; SW1 ; None ; None ; 3.600 ns ;
+------------------------------------------+--------+--------+------------+----------+----------------------------+----------------------------+--------------------------+
+-----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+-------------+------------+
; N/A ; None ; 23.800 ns ; wire_1 ; Latch_EN ; f1hz ;
; N/A ; None ; 23.800 ns ; wire_1 ; Latch_EN ; f10hz ;
; N/A ; None ; 23.800 ns ; wire_1 ; Latch_EN ; SW1 ;
; N/A ; None ; 23.800 ns ; wire_2 ; Latch_EN ; f1hz ;
; N/A ; None ; 23.800 ns ; wire_2 ; Latch_EN ; f10hz ;
; N/A ; None ; 23.800 ns ; wire_2 ; Latch_EN ; SW1 ;
; N/A ; None ; 19.200 ns ; wire_1 ; Latch_EN ; f100hz ;
; N/A ; None ; 19.200 ns ; wire_1 ; Latch_EN ; SW2 ;
; N/A ; None ; 19.200 ns ; wire_2 ; Latch_EN ; f100hz ;
; N/A ; None ; 19.200 ns ; wire_2 ; Latch_EN ; SW2 ;
; N/A ; None ; 19.200 ns ; wire_2 ; Counter_Clr ; f1hz ;
; N/A ; None ; 19.200 ns ; wire_2 ; Counter_Clr ; f10hz ;
; N/A ; None ; 19.200 ns ; wire_2 ; Counter_Clr ; SW1 ;
; N/A ; None ; 19.200 ns ; wire_1 ; Counter_EN ; f1hz ;
; N/A ; None ; 19.200 ns ; wire_1 ; Counter_EN ; f10hz ;
; N/A ; None ; 19.200 ns ; wire_1 ; Counter_EN ; SW1 ;
; N/A ; None ; 17.700 ns ; wire_1 ; Latch_EN ; SW0 ;
; N/A ; None ; 17.700 ns ; wire_2 ; Latch_EN ; SW0 ;
; N/A ; None ; 14.600 ns ; wire_2 ; Counter_Clr ; f100hz ;
; N/A ; None ; 14.600 ns ; wire_2 ; Counter_Clr ; SW2 ;
; N/A ; None ; 14.600 ns ; wire_1 ; Counter_EN ; f100hz ;
; N/A ; None ; 14.600 ns ; wire_1 ; Counter_EN ; SW2 ;
; N/A ; None ; 13.100 ns ; wire_2 ; Counter_Clr ; SW0 ;
; N/A ; None ; 13.100 ns ; wire_1 ; Counter_EN ; SW0 ;
+-------+--------------+------------+--------+-------------+------------+
+----------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-----------+
; N/A ; None ; 8.100 ns ; SW2 ; dp_s100hz ;
; N/A ; None ; 8.100 ns ; SW1 ; dp_s100hz ;
; N/A ; None ; 8.100 ns ; SW0 ; dp_s100hz ;
; N/A ; None ; 8.100 ns ; SW2 ; dp_s10hz ;
; N/A ; None ; 8.100 ns ; SW1 ; dp_s10hz ;
; N/A ; None ; 8.100 ns ; SW0 ; dp_s10hz ;
; N/A ; None ; 8.100 ns ; SW2 ; dp_s1hz ;
; N/A ; None ; 8.100 ns ; SW1 ; dp_s1hz ;
; N/A ; None ; 8.100 ns ; SW0 ; dp_s1hz ;
+-------+-------------------+-----------------+------+-----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Mon Jul 17 20:29:28 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off gate_control -c gate_control
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
Info: Node "fref~106"
Info: Found combinational loop of 1 nodes
Info: Node "dp_s100hz$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "dp_s10hz$latch~10"
Info: Found combinational loop of 1 nodes
Info: Node "dp_s1hz$latch~10"
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "SW2" is an undefined clock
Info: Assuming node "f100hz" is an undefined clock
Info: Assuming node "SW1" is an undefined clock
Info: Assuming node "f10hz" is an undefined clock
Info: Assuming node "f1hz" is an undefined clock
Info: Assuming node "SW0" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "fref~106" as buffer
Info: Detected gated clock "always0~10sexp" as buffer
Info: Detected gated clock "fref~94" as buffer
Info: Detected gated clock "fref~100" as buffer
Info: Clock "SW2" has Internal fmax of 48.54 MHz between source register "wire_1" and destination register "wire_2" (period= 20.6 ns)
Info: + Longest register to register delay is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
Info: Total cell delay = 2.600 ns ( 72.22 % )
Info: Total interconnect delay = 1.000 ns ( 27.78 % )
Info: - Smallest clock skew is -4.600 ns
Info: + Shortest clock path from clock "SW2" to destination register is 8.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'
Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
Info: Loc. = LC4; Node "fref~106"
Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
Info: Total cell delay = 7.500 ns ( 88.24 % )
Info: Total interconnect delay = 1.000 ns ( 11.76 % )
Info: - Longest clock path from clock "SW2" to source register is 13.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'
Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
Info: Loc. = LC4; Node "fref~106"
Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
Info: Total cell delay = 11.100 ns ( 84.73 % )
Info: Total interconnect delay = 2.000 ns ( 15.27 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Micro setup delay of destination is 0.800 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "f100hz" has Internal fmax of 87.72 MHz between source register "wire_1" and destination register "wire_2" (period= 11.4 ns)
Info: + Longest register to register delay is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
Info: Total cell delay = 2.600 ns ( 72.22 % )
Info: Total interconnect delay = 1.000 ns ( 27.78 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "f100hz" to destination register is 13.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f100hz'
Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
Info: Loc. = LC4; Node "fref~106"
Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
Info: Total cell delay = 11.100 ns ( 84.73 % )
Info: Total interconnect delay = 2.000 ns ( 15.27 % )
Info: - Longest clock path from clock "f100hz" to source register is 13.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f100hz'
Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
Info: Loc. = LC4; Node "fref~106"
Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
Info: Total cell delay = 11.100 ns ( 84.73 % )
Info: Total interconnect delay = 2.000 ns ( 15.27 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Micro setup delay of destination is 0.800 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "SW1" has Internal fmax of 33.56 MHz between source register "wire_1" and destination register "wire_2" (period= 29.8 ns)
Info: + Longest register to register delay is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
Info: Total cell delay = 2.600 ns ( 72.22 % )
Info: Total interconnect delay = 1.000 ns ( 27.78 % )
Info: - Smallest clock skew is -9.200 ns
Info: + Shortest clock path from clock "SW1" to destination register is 8.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'
Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
Info: Loc. = LC4; Node "fref~106"
Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'
Info: Total cell delay = 7.500 ns ( 88.24 % )
Info: Total interconnect delay = 1.000 ns ( 11.76 % )
Info: - Longest clock path from clock "SW1" to source register is 17.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'
Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'
Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'
Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'
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