gate_control.tan.summary

verilog写的数字频率计的控制模块,对程序进行控制

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.800 ns
From           : wire_2
To             : Latch_EN
From Clock     : SW1
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.100 ns
From           : SW0
To             : dp_s1hz
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'SW1'
Slack          : N/A
Required Time  : None
Actual Time    : 33.56 MHz ( period = 29.800 ns )
From           : wire_1
To             : wire_2
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 0

Type           : Clock Setup: 'SW2'
Slack          : N/A
Required Time  : None
Actual Time    : 48.54 MHz ( period = 20.600 ns )
From           : wire_1
To             : wire_2
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 0

Type           : Clock Setup: 'SW0'
Slack          : N/A
Required Time  : None
Actual Time    : 56.82 MHz ( period = 17.600 ns )
From           : wire_1
To             : wire_2
From Clock     : SW0
To Clock       : SW0
Failed Paths   : 0

Type           : Clock Setup: 'f1hz'
Slack          : N/A
Required Time  : None
Actual Time    : 87.72 MHz ( period = 11.400 ns )
From           : wire_1
To             : wire_2
From Clock     : f1hz
To Clock       : f1hz
Failed Paths   : 0

Type           : Clock Setup: 'f10hz'
Slack          : N/A
Required Time  : None
Actual Time    : 87.72 MHz ( period = 11.400 ns )
From           : wire_1
To             : wire_2
From Clock     : f10hz
To Clock       : f10hz
Failed Paths   : 0

Type           : Clock Setup: 'f100hz'
Slack          : N/A
Required Time  : None
Actual Time    : 87.72 MHz ( period = 11.400 ns )
From           : wire_1
To             : wire_2
From Clock     : f100hz
To Clock       : f100hz
Failed Paths   : 0

Type           : Clock Hold: 'SW1'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : wire_1
To             : wire_2
From Clock     : SW1
To Clock       : SW1
Failed Paths   : 2

Type           : Clock Hold: 'SW2'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : wire_1
To             : wire_2
From Clock     : SW2
To Clock       : SW2
Failed Paths   : 2

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 4

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