dispdecoder.hier_info

verilog写的数字频率计的显示模块,可以

|dispdecoder
data_in[0] => Decoder~0.IN3
data_in[1] => Decoder~0.IN2
data_in[2] => Decoder~0.IN1
data_in[3] => Decoder~0.IN0
disp_select[0] => always1~4.IN0
disp_select[0] => Decoder~1.IN2
disp_select[1] => reduce_nor~0.IN1
disp_select[1] => always1~1.IN0
disp_select[1] => reduce_nor~2.IN0
disp_select[1] => Decoder~1.IN1
disp_select[2] => reduce_nor~0.IN0
disp_select[2] => reduce_nor~1.IN0
disp_select[2] => always1~5.IN0
disp_select[2] => Decoder~1.IN0
dp_s1hz => always1~6.IN0
dp_s10hz => always1~2.IN0
dp_s10hz => always1~20.IN0
dp_s100hz => always1~0.IN0
dp_s100hz => always1~18.IN0
Q5[0] => reduce_nor~3.IN3
Q5[1] => reduce_nor~3.IN2
Q5[2] => reduce_nor~3.IN1
Q5[3] => reduce_nor~3.IN0
Q4[0] => reduce_nor~4.IN3
Q4[1] => reduce_nor~4.IN2
Q4[2] => reduce_nor~4.IN1
Q4[3] => reduce_nor~4.IN0
Q3[0] => reduce_nor~5.IN3
Q3[1] => reduce_nor~5.IN2
Q3[2] => reduce_nor~5.IN1
Q3[3] => reduce_nor~5.IN0
Q2[0] => reduce_nor~6.IN3
Q2[1] => reduce_nor~6.IN2
Q2[2] => reduce_nor~6.IN1
Q2[3] => reduce_nor~6.IN0
Q1[0] => reduce_nor~7.IN3
Q1[1] => reduce_nor~7.IN2
Q1[2] => reduce_nor~7.IN1
Q1[3] => reduce_nor~7.IN0
Q0[0] => ~NO_FANOUT~
Q0[1] => ~NO_FANOUT~
Q0[2] => ~NO_FANOUT~
Q0[3] => ~NO_FANOUT~
counter_out => always1~12.IN0
data_out[0] <= data_out[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
dp <= dp~0.DB_MAX_OUTPUT_PORT_TYPE