dispdecoder.map.summary

verilog写的数字频率计的显示模块,可以

Flow Status : Successful - Mon Jul 17 22:27:22 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : dispdecoder
Top-level Entity Name : dispdecoder
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 10
Total pins : 43