ddr_data_path.srs

DDR（双速率）SDRAM控制器参考设计verilog代码

#
#
#
# Created by Synplify Verilog HDL Compiler version 5.3.0 from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sat May 20 12:17:51 2000
#
#
#OPTIONS:"|-ram|-I|D:\\Program Files\\synplicity_53\\synplify\\lib|-sm|-fid2|-sharing|on|-encrypt|-ui"
#CUR:"D:\\Program Files\\synplicity_53\\synplify\\bin\\c_ver.exe":944594346l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\ddr_sdram.v":958824465l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\params.v":958344460l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\params.v":958344460l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\pll1.v":958824158l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\ddr_control_interface.v":958346108l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\params.v":958344460l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\ddr_command.v":958347904l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\params.v":958344460l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\ddr_data_path.v":958447228l
#CUR:"d:\\projects\\altera\\lpcores\\ddr\\release\\v1_1\\synthesis\\synplicity\\params.v":958344460l
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_sdram.v"; # file 0
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"; # file 1
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"; # file 2
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\pll1.v"; # file 3
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_control_interface.v"; # file 4
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"; # file 5
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v"; # file 6
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"; # file 7
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v"; # file 8
f "d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\params.v"; # file 9
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@bR@cd:nj:4::cn4x6RRFODOR	4OODF	
4;y--------------------------------
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b@:@c4:d(.4j:dd(:.MRN8WPR) QaqR4dWa)Q dq4R7BvrR49k_M4Brv7jk9RMB4_v.7r9b;
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b@:@c4:(6j(:46R:68sVVR_1BAdpr:Rj91AB_p:rdj19RBp_A_d(r:Rj9BRpik_M4)  1a;_h
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Rc@@:n4j:4j:j6n:RV8VsmRpqv7_mR7 p7mq_7vm mRpqv7_m47 dpRBiMRk4 _)1_ ahb;
Rc@@:n4j:4j:j6n:RV8VsmRhumRhumRhuR4dBRpik_M4)  1a;_h
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Rc@@:.4n::.44:n.6NdRMR8Pp7mq_t) .R4dp7mq_t) .R4dBrv7jB9Rv47r9vRB79r.R4kM_qpm7 _)t
.;b@R@cc:..4:d:..c:Rc4NPM8R4kM_4kM__1BAkpRMk4_M14_Bp_AR4kM__1BAjpr9MRk4B_1_rAp4R9
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Rc@@:n4j:4j:j6n:RV8VsmRpq)7_ Rt.p7mq_t) .mRpq)7_ 4t.dpRBiMRk4 _)1_ ahb;
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@bR@.c:c..:jc:.g4:dRPFsR4kM_l0HCxs_C4sFdR_4k_M40CHlsC_xsdF4_04RHslC_sxCFR4d)_ wq;Bi
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Rc@@:..c::.j.:cgdN4RMR8P0CHlsC_xscF4Rl0HCxs_C4sFc R)wB_qiMRk4H_0l_CsxFCs4
d;b@R@cc:.4d:d:4.c:Rc4NR88k_M40CHlsr_44j6:9MRk4H_0l_Cs46r4:Rj90CHls6r4:Rj9k_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_,Apk_M4k_M4k_M41AB_pM,k4M_k4M_k4B_1_;Ap
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b@:@c.:.Uj.:.UR:68sVVRl0HCxs_CRsF0CHlsC_xs0FRHslC_sxCFR_UBRpik_M4)  1a;_h
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---------------------------------M-
Rn@@::dj(j:d:R4(I	FsRs88_lOFl8NMRsPCHoDF;P
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Rn@@::(jd(.:jn:dRPHMR4kM__1B)4Br:Rj9k_M41)B_B:r4j19RBB_)rj4:9b;
Rn@@::(.d(.:.n:dRPHMR4kM__1BukvRM14_Bv_uR_1Bu
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4;b@R@nc:dj::Ud:cj4HdRMkPRM84_Fs_IHN0C4R_4k_M48IF_sCH0N44_R_8FI0sHC;N4
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C;b@R@nn:d(U:.:(dn:R(nFRsPBh1_4BUR14_hUFR8_VsCsEC#R_8FbOsCEoNsCFR8_NDF8F_l8
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