ddr_data_path.xrf

DDR（双速率）SDRAM控制器参考设计verilog代码

instance = comp, DQS_tri_0_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_1_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_2_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_3_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_4_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_5_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_6_, , ddr_sdram, 1, 71:32:71:34
instance = comp, DQS_tri_7_, , ddr_sdram, 1, 71:32:71:34
instance = comp, CAS_N_0, , ddr_sdram, 1, 230:0:230:5
instance = comp, CKE_0, , ddr_sdram, 1, 230:0:230:5
instance = comp, RAS_N_0, , ddr_sdram, 1, 230:0:230:5
instance = comp, WE_N_0, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_0_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_1_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_2_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_3_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_4_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_5_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_6_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_7_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_8_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_9_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_10_, , ddr_sdram, 1, 230:0:230:5
instance = comp, SA_11_, , ddr_sdram, 1, 230:0:230:5
instance = comp, CS_N_0_, , ddr_sdram, 1, 230:0:230:5
instance = comp, CS_N_1_, , ddr_sdram, 1, 230:0:230:5
instance = comp, BA_0_, , ddr_sdram, 1, 230:0:230:5
instance = comp, BA_1_, , ddr_sdram, 1, 230:0:230:5
instance = comp, data_path1_false, , ddr_sdram, 1, 1:1:1:2
instance = comp, data_path1_true, , ddr_sdram, 1, 1:1:1:2
design_name=ddr_control_interface
instance = comp, un1_timer_zero13_1_0_0_Z, , ddr_control_interface, 4, 242:20:249:31
instance = comp, un1_un1_SC_BL, , ddr_control_interface, 4, 242:31:242:41
instance = comp, un1_timer_zero13_1_0_0_and2_G_55, , ddr_control_interface, 4, 242:20:249:31
instance = comp, un1_timer_zero13_1_0_0_and2_G_51, , ddr_control_interface, 4, 242:20:249:31
instance = comp, un1_timer_zero13_1_0_0_and2_G_54, , ddr_control_interface, 4, 242:20:249:31
instance = comp, un1_timer_zero13_1_0_0_and2_G_53, , ddr_control_interface, 4, 242:20:249:31
instance = comp, G_1_i_and2_0_and2_Z, , ddr_control_interface, 1, 121:22:121:29
instance = comp, SC_CL_rep1_0_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_PM_0, , ddr_control_interface, 4, 175:0:175:5
instance = comp, LOAD_MODE_0, , ddr_control_interface, 4, 106:0:106:5
instance = comp, PRECHARGE_0, , ddr_control_interface, 4, 106:0:106:5
instance = comp, READA_0, , ddr_control_interface, 4, 106:0:106:5
instance = comp, REFRESH_0, , ddr_control_interface, 4, 106:0:106:5
instance = comp, WRITEA_0, , ddr_control_interface, 4, 106:0:106:5
instance = comp, LOAD_REG1_Z, , ddr_control_interface, 4, 106:0:106:5
instance = comp, LOAD_REG2_Z, , ddr_control_interface, 4, 106:0:106:5
instance = comp, CMD_ACK_0, , ddr_control_interface, 4, 209:0:209:5
instance = comp, REF_REQ_0, , ddr_control_interface, 4, 228:0:228:5
instance = comp, REF_PER_0_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_1_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_2_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_3_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_4_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_5_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_6_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_7_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_8_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_9_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_10_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_11_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_12_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_13_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_14_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, REF_PER_15_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_BL_0_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_BL_1_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_BL_2_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_BL_3_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_RC_0_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_RC_1_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SC_CL_0_, , ddr_control_interface, 4, 175:0:175:5
instance = comp, SADDR_0_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_1_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_2_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_3_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_4_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_5_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_6_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_7_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_8_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_9_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_10_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_11_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_12_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_13_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_14_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_15_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_16_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_17_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_18_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_19_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_20_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, SADDR_21_, , ddr_control_interface, 4, 106:0:106:5
instance = comp, timer_15_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_14_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_13_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_12_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_11_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_10_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_9_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_8_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_7_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_6_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_5_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_4_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_3_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_2_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_1_, , ddr_control_interface, 4, 228:0:228:5
instance = comp, timer_0_, , ddr_control_interface, 4, 228:0:228:5
design_name=ddr_command
instance = comp, G_149_Z, , ddr_command, 1, 144:12:144:19
instance = comp, G_117_Z, , ddr_command, 5, 193:21:194:36
instance = comp, G_150_Z, , ddr_command, 1, 144:12:144:19
instance = comp, G_142_Z, , ddr_command, 1, 144:12:144:19
instance = comp, un1_un1_SC_RC_i_0_Z, , ddr_command, 5, 291:24:291:25
instance = comp, un1_do_rw20_3_i_0_Z, , ddr_command, 5, 291:24:291:25
instance = comp, CM_ACK14_i_0_Z, , ddr_command, 5, 321:20:324:40
instance = comp, CM_ACK14_i_0_and2_Z, , ddr_command, 5, 321:20:324:40
instance = comp, un1_un1_un1_oe_shift17_i_0_Z, , ddr_command, 5, 243:28:247:42
instance = comp, un1_un1_un1_oe_shift17_i_0_and2_Z, , ddr_command, 5, 243:28:247:42
instance = comp, SA_8_2_0_a0_i_Z, , ddr_command, 5, 354:24:354:25
instance = comp, SA20_i_and2_Z, , ddr_command, 5, 359:29:359:57
instance = comp, G_151_Z, , ddr_command, 5, 241:20:241:34
instance = comp, G_173_Z, , ddr_command, 1, 144:12:144:19
instance = comp, WE_N_12_0_and2_0_Z, , ddr_command, 5, 341:16:341:17
instance = comp, G_149_rep0_Z, , ddr_command, 1, 144:12:144:19
instance = comp, CKE_0, , ddr_command, 5, 340:8:340:13
instance = comp, do_load_mode_Z, , ddr_command, 5, 135:0:135:5
instance = comp, do_precharge_Z, , ddr_command, 5, 135:0:135:5
instance = comp, do_reada_Z, , ddr_command, 5, 135:0:135:5
instance = comp, do_writea1_Z, , ddr_command, 5, 135:0:135:5
instance = comp, rp_done_Z, , ddr_command, 5, 135:0:135:5
instance = comp, oe3_Z, , ddr_command, 5, 230:0:230:5
instance = comp, oe4_Z, , ddr_command, 5, 230:0:230:5
instance = comp, do_refresh_Z, , ddr_command, 5, 135:0:135:5
instance = comp, RAS_N_0, , ddr_command, 5, 340:8:340:13
instance = comp, oe1_Z, , ddr_command, 5, 230:0:230:5
instance = comp, oe2_Z, , ddr_command, 5, 230:0:230:5
instance = comp, command_done_Z, , ddr_command, 5, 135:0:135:5
instance = comp, rw_flag_Z, , ddr_command, 5, 135:0:135:5
instance = comp, OE_0, , ddr_command, 5, 230:0:230:5
instance = comp, do_rw_Z, , ddr_command, 5, 278:0:278:5
instance = comp, CM_ACK_0, , ddr_command, 5, 310:0:310:5
instance = comp, REF_ACK_0, , ddr_command, 5, 310:0:310:5
instance = comp, CAS_N_0, , ddr_command, 5, 340:8:340:13
instance = comp, WE_N_0, , ddr_command, 5, 340:8:340:13
instance = comp, oe_shift_0_, , ddr_command, 5, 230:0:230:5
instance = comp, oe_shift_1_, , ddr_command, 5, 230:0:230:5
instance = comp, oe_shift_2_, , ddr_command, 5, 230:0:230:5
instance = comp, oe_shift_3_, , ddr_command, 5, 230:0:230:5
instance = comp, SA_0_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_1_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_2_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_3_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_4_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_5_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_6_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_7_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_8_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_9_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_10_, , ddr_command, 5, 340:8:340:13
instance = comp, SA_11_, , ddr_command, 5, 340:8:340:13
instance = comp, command_delay_0_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_1_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_2_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_3_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_4_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_5_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_6_, , ddr_command, 5, 135:0:135:5
instance = comp, command_delay_7_, , ddr_command, 5, 135:0:135:5
instance = comp, CS_N_0_, , ddr_command, 5, 340:8:340:13
instance = comp, CS_N_1_, , ddr_command, 5, 340:8:340:13
instance = comp, rw_shift_0_, , ddr_command, 5, 278:0:278:5
instance = comp, rw_shift_1_, , ddr_command, 5, 278:0:278:5
instance = comp, BA_0_, , ddr_command, 5, 340:8:340:13
instance = comp, BA_1_, , ddr_command, 5, 340:8:340:13
instance = comp, rp_shift_0_, , ddr_command, 5, 135:0:135:5
instance = comp, rp_shift_1_, , ddr_command, 5, 135:0:135:5
instance = comp, rp_shift_2_, , ddr_command, 5, 135:0:135:5
instance = comp, rp_shift_3_, , ddr_command, 5, 135:0:135:5
design_name=ddr_data_path
instance = comp, delayed_OE_0, , ddr_data_path, 6, 193:0:193:5
instance = comp, dqs2a_0, , ddr_data_path, 6, 193:0:193:5
instance = comp, dqs2b_0, , ddr_data_path, 6, 193:0:193:5
instance = comp, hi_lo_Z, , ddr_data_path, 6, 155:0:155:5
instance = comp, dqs1a_Z, , ddr_data_path, 6, 193:0:193:5
instance = comp, dqs1b_Z, , ddr_data_path, 6, 193:0:193:5
instance = comp, DQM_0_, , ddr_data_path, 6, 155:0:155:5
instance = comp, DQM_1_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_0_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_1_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_2_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_3_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_4_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_5_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_6_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_7_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_8_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_9_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_10_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_11_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_12_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_13_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_14_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dq1_15_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dm1_0_, , ddr_data_path, 6, 155:0:155:5
instance = comp, dm1_1_, , ddr_data_path, 6, 155:0:155:5
instance = comp, din2x_1_0_, , ddr_data_path, 6, 193:0:193:5
instance = comp, din2x_1_1_, , ddr_data_path, 6, 193:0:193:5
instance = comp, din2x_1_2_, , ddr_data_path, 6, 193:0:193:5
instance = comp, din2x_1_3_, , ddr_data_path, 6, 193:0:193:5
instance = comp, din2x_1_4_, , ddr_data_path, 6, 193:0:193:5