ddr_sdram.tcl

DDR（双速率）SDRAM控制器参考设计verilog代码

cmp add_assignment "" "" "" ROOT "|ddr_sdram"
cmp add_assignment "" "" "" FAMILY "APEX20KE"
cmp add_assignment "ddr_sdram" "" "" DEVICE "EP20K400EFC672-1X"
project add_assignment "ddr_sdram" "" "" "|CLK" "GLOBAL_SIGNAL" "ON"
project add_assignment "" "CLK_setting" "" "" "FMAX_REQUIREMENT" "100.0MHZ"
project add_assignment "ddr_sdram" "" "" "|CLK" "USE_CLOCK_SETTINGS" "CLK_setting"
project add_assignment "" "CLK_setting" "" "" "DUTY_CYCLE" "50"