ddr_data_path.tlg

来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· TLG 代码 · 共 28 行

Selecting top level module ddr_sdram
Synthesizing module pll1
Synthesizing module ddr_control_interface
Synthesizing module ddr_command
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":111:32:111:37|No assignment to do_act
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Ignoring missing reset value for signal oe4. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Ignoring missing reset value for signal oe3. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[7] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":278:0:278:5|Optimizing register bit rw_shift[3] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[6] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":278:0:278:5|Optimizing register bit rw_shift[2] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[5] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":230:0:230:5|Optimizing register bit oe_shift[4] to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":63:32:63:34|Input NOP is unused
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":69:32:69:36|Input SC_CL is unused
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_command.v":71:32:71:37|Input SC_RRD is unused
Synthesizing module ddr_data_path
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":77:32:77:36|No assignment to dqs3a
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":80:32:80:36|No assignment to dqs3b
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":97:32:97:39|No assignment to din2x_1a
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":193:0:193:5|Ignoring missing reset value for signal d2_OE. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":155:0:155:5|Ignoring missing reset value for signal din2a[31:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":155:0:155:5|Ignoring missing reset value for signal dq2[15:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":155:0:155:5|Ignoring missing reset value for signal dmin2a[3:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":155:0:155:5|Feedback mux created for signal dm1[1:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\v1_1\synthesis\synplicity\ddr_data_path.v":106:0:106:5|Ignoring missing reset value for signal DATAOUT[31:0]. Did you forget the set/reset assignment for this signal?
Synthesizing module ddr_sdram