ddr_sdram.prj

DDR（双速率）SDRAM控制器参考设计verilog代码

#-- Synplicity, Inc.
#-- Synplify version 5.3.1
#-- Project file D:\Projects\altera\lpcores\ddr\release\V1_1\synthesis\synplicity\ddr_sdram.prj
#-- Written on Mon May 22 12:07:01 2000

#device options
set_option -technology APEX20K
set_option -part EP20K400E
set_option -package FC672
set_option -speed_grade -1X

#add_file options
add_file -verilog "ddr_sdram.v"
add_file -verilog "params.v"
add_file -verilog "pll1.v"
add_file -verilog "ddr_control_interface.v"
add_file -verilog "ddr_command.v"
add_file -constraint "ddr_sdram.sdc"
add_file -verilog "ddr_data_path.v"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
set_option -resource_sharing true

#map options
set_option -frequency 200.000
set_option -disable_io_insertion false
set_option -map_logic true
set_option -cliquing false

#simulation options
set_option -write_verilog false
set_option -write_vhdl false

#automatic place and route (vendor) options
set_option -write_apr_constraint true

#MTI Cross Probe options
set_option -mti_root ""

#set result format/file last
project -result_file "ddr_sdram.vqm"