_primary.vhd

DDR（双速率）SDRAM控制器参考设计verilog代码

library verilog;
use verilog.vl_types.all;
entity ddr_data_path is
    port(
        clk100          : in     vl_logic;
        clk200          : in     vl_logic;
        reset_n         : in     vl_logic;
        oe              : in     vl_logic;
        datain          : in     vl_logic_vector(31 downto 0);
        dm              : in     vl_logic_vector(3 downto 0);
        dataout         : out    vl_logic_vector(31 downto 0);
        dqin            : in     vl_logic_vector(15 downto 0);
        dqout           : out    vl_logic_vector(15 downto 0);
        dqm             : out    vl_logic_vector(1 downto 0);
        dqs             : inout  vl_logic_vector(1 downto 0);
        sc_cl           : in     vl_logic_vector(1 downto 0);
        dqoe            : out    vl_logic
    );
end ddr_data_path;