_primary.vhd

DDR（双速率）SDRAM控制器参考设计verilog代码

library verilog;
use verilog.vl_types.all;
entity ddr_command is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        saddr           : in     vl_logic_vector(21 downto 0);
        nop             : in     vl_logic;
        reada           : in     vl_logic;
        writea          : in     vl_logic;
        refresh         : in     vl_logic;
        precharge       : in     vl_logic;
        load_mode       : in     vl_logic;
        sc_cl           : in     vl_logic_vector(1 downto 0);
        sc_rc           : in     vl_logic_vector(1 downto 0);
        sc_rrd          : in     vl_logic_vector(3 downto 0);
        sc_pm           : in     vl_logic;
        sc_bl           : in     vl_logic_vector(3 downto 0);
        ref_req         : in     vl_logic;
        ref_ack         : out    vl_logic;
        cm_ack          : out    vl_logic;
        oe              : out    vl_logic;
        sa              : out    vl_logic_vector(11 downto 0);
        ba              : out    vl_logic_vector(1 downto 0);
        cs_n            : out    vl_logic_vector(1 downto 0);
        cke             : out    vl_logic;
        ras_n           : out    vl_logic;
        cas_n           : out    vl_logic;
        we_n            : out    vl_logic
    );
end ddr_command;