readme.txt

来自「DDR（双速率）SDRAM控制器参考设计verilog代码」· 文本 代码 · 共 10 行

File/Directory				Description
=============================================================================
\doc				DDR SDRAM reference design documentation
\model				Contains the verilog SDRAM model
\route				Contains the Quartus 2000.05 project files a routed controller design
\simulation			Contains the verilog testbench, modelsim project file, and library
\source				Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity		Contains all synplicity project files associated with synthesizing the reference design