booth_mult_timesim.v

64位乘法器源码verilog,经过验证测试

// Xilinx Verilog netlist produced by netgen application (version G.31a)
// Command      : -intstyle ise -s 6 -pcf booth_mult.pcf -ngm booth_mult.ngm -w -ofmt verilog -sim booth_mult.ncd booth_mult_timesim.v 
// Input file   : booth_mult.ncd
// Output file  : booth_mult_timesim.v
// Design name  : booth_mult
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : 2s50tq144-6 (PRODUCTION 1.27 2003-12-13)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module booth_mult (
p, y, x
);
  output [14 : 0] p;
  input [7 : 0] y;
  input [7 : 0] x;
  wire y_2_IBUF;
  wire x_6_IBUF;
  wire y_3_IBUF;
  wire x_7_IBUF;
  wire y_4_IBUF;
  wire y_5_IBUF;
  wire y_6_IBUF;
  wire y_7_IBUF;
  wire p_1_OBUF;
  wire p_2_OBUF;
  wire p_3_OBUF;
  wire p_4_OBUF;
  wire p_5_OBUF;
  wire p_6_OBUF;
  wire p_7_OBUF;
  wire p_8_OBUF;
  wire p_9_OBUF;
  wire op3;
  wire addsub3_Madd_s_inst_cy_27;
  wire \addsub3_y_xor[0] ;
  wire addsub3_Madd_s_inst_cy_29;
  wire addsub3_Madd_s_inst_cy_31;
  wire addsub3_Madd_s_inst_cy_33;
  wire addsub3_Madd_s_inst_cy_35;
  wire \addsub3_y_xor[10] ;
  wire op2;
  wire addsub2_Madd_s_inst_cy_15;
  wire \addsub2_y_xor[0] ;
  wire addsub2_Madd_s_inst_cy_17;
  wire addsub2_Madd_s_inst_cy_19;
  wire addsub2_Madd_s_inst_cy_21;
  wire addsub2_Madd_s_inst_cy_23;
  wire \addsub2_y_xor[12] ;
  wire addsub2_Madd_s_inst_cy_25;
  wire op4;
  wire addsub4_Madd_s_inst_cy_37;
  wire addsub4_Madd_s_inst_cy_39;
  wire addsub4_Madd_s_inst_cy_41;
  wire p_10_OBUF;
  wire p_11_OBUF;
  wire addsub4_Madd_s_inst_cy_43;
  wire p_12_OBUF;
  wire p_13_OBUF;
  wire addsub1_Madd_s_inst_cy_1;
  wire x_1_IBUF;
  wire x_0_IBUF;
  wire y_0_IBUF;
  wire GLOBAL_LOGIC0;
  wire \addsub1_y_xor[1] ;
  wire addsub1_Madd_s_inst_cy_3;
  wire y_1_IBUF;
  wire addsub1_Madd_s_inst_cy_5;
  wire addsub1_Madd_s_inst_cy_7;
  wire addsub1_Madd_s_inst_cy_9;
  wire addsub1_Madd_s_inst_cy_11;
  wire addsub1_Madd_s_inst_cy_13;
  wire x_3_IBUF;
  wire x_4_IBUF;
  wire x_5_IBUF;
  wire x_2_IBUF;
  wire N3330;
  wire p_14_OBUF;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \y<2>/IBUF ;
  wire \x<6>/IBUF ;
  wire \y<3>/IBUF ;
  wire \x<7>/IBUF ;
  wire \y<4>/IBUF ;
  wire \y<5>/IBUF ;
  wire \y<6>/IBUF ;
  wire \y<7>/IBUF ;
  wire \p<0>/ENABLE ;
  wire \p<0>/TORGTS ;
  wire \p<0>/OUTMUX ;
  wire \p<1>/ENABLE ;
  wire \p<1>/TORGTS ;
  wire \p<1>/OUTMUX ;
  wire \p<2>/ENABLE ;
  wire \p<2>/TORGTS ;
  wire \p<2>/OUTMUX ;
  wire \p<3>/ENABLE ;
  wire \p<3>/TORGTS ;
  wire \p<3>/OUTMUX ;
  wire \p<4>/ENABLE ;
  wire \p<4>/TORGTS ;
  wire \p<4>/OUTMUX ;
  wire \p<5>/ENABLE ;
  wire \p<5>/TORGTS ;
  wire \p<5>/OUTMUX ;
  wire \p<6>/ENABLE ;
  wire \p<6>/TORGTS ;
  wire \p<6>/OUTMUX ;
  wire \p<7>/ENABLE ;
  wire \p<7>/TORGTS ;
  wire \p<7>/OUTMUX ;
  wire \p<8>/ENABLE ;
  wire \p<8>/TORGTS ;
  wire \p<8>/OUTMUX ;
  wire \p<9>/ENABLE ;
  wire \p<9>/TORGTS ;
  wire \p<9>/OUTMUX ;
  wire addsub3_Madd_s_inst_lut2_28;
  wire \p_4_OBUF/XORF ;
  wire \p_4_OBUF/CYMUXG ;
  wire \p_4_OBUF/XORG ;
  wire addsub3_Madd_s_inst_lut2_29;
  wire addsub3_Madd_s_inst_cy_26;
  wire \p_4_OBUF/CYINIT ;
  wire addsub3_Madd_s_inst_lut2_30;
  wire \p3<2>/XORF ;
  wire \p3<2>/CYMUXG ;
  wire \p3<2>/XORG ;
  wire addsub3_Madd_s_inst_lut2_31;
  wire addsub3_Madd_s_inst_cy_28;
  wire \p3<2>/CYINIT ;
  wire addsub3_Madd_s_inst_lut2_32;
  wire \p3<4>/XORF ;
  wire \p3<4>/CYMUXG ;
  wire \p3<4>/XORG ;
  wire addsub3_Madd_s_inst_lut2_33;
  wire addsub3_Madd_s_inst_cy_30;
  wire \p3<4>/CYINIT ;
  wire addsub3_Madd_s_inst_lut2_34;
  wire \p3<6>/XORF ;
  wire \p3<6>/CYMUXG ;
  wire \p3<6>/XORG ;
  wire addsub3_Madd_s_inst_lut2_35;
  wire addsub3_Madd_s_inst_cy_32;
  wire \p3<6>/CYINIT ;
  wire addsub3_Madd_s_inst_lut2_36;
  wire \p3<8>/XORF ;
  wire \p3<8>/CYMUXG ;
  wire \p3<8>/XORG ;
  wire addsub3_Madd_s_inst_lut2_37;
  wire addsub3_Madd_s_inst_cy_34;
  wire \p3<8>/CYINIT ;
  wire addsub2_Madd_s_inst_lut2_15;
  wire \p_2_OBUF/XORF ;
  wire \p_2_OBUF/CYMUXG ;
  wire \p_2_OBUF/XORG ;
  wire addsub2_Madd_s_inst_lut2_16;
  wire addsub2_Madd_s_inst_cy_14;
  wire \p_2_OBUF/CYINIT ;
  wire addsub2_Madd_s_inst_lut2_17;
  wire \p2<2>/XORF ;
  wire \p2<2>/CYMUXG ;
  wire \p2<2>/XORG ;
  wire addsub2_Madd_s_inst_lut2_18;
  wire addsub2_Madd_s_inst_cy_16;
  wire \p2<2>/CYINIT ;
  wire addsub2_Madd_s_inst_lut2_19;
  wire \p2<4>/XORF ;
  wire \p2<4>/CYMUXG ;
  wire \p2<4>/XORG ;
  wire addsub2_Madd_s_inst_lut2_20;
  wire addsub2_Madd_s_inst_cy_18;
  wire \p2<4>/CYINIT ;
  wire addsub2_Madd_s_inst_lut2_21;
  wire \p2<6>/XORF ;
  wire \p2<6>/CYMUXG ;
  wire \p2<6>/XORG ;
  wire addsub2_Madd_s_inst_lut2_22;
  wire addsub2_Madd_s_inst_cy_20;
  wire \p2<6>/CYINIT ;
  wire addsub2_Madd_s_inst_lut2_23;
  wire \p2<8>/XORF ;
  wire \p2<8>/CYMUXG ;
  wire \p2<8>/XORG ;
  wire addsub2_Madd_s_inst_lut2_24;
  wire addsub2_Madd_s_inst_cy_22;
  wire \p2<8>/CYINIT ;
  wire addsub2_Madd_s_inst_lut2_25;
  wire \p2<10>/XORF ;
  wire \p2<10>/CYMUXG ;
  wire \p2<10>/XORG ;
  wire addsub2_Madd_s_inst_lut2_26;
  wire addsub2_Madd_s_inst_cy_24;
  wire \p2<10>/CYINIT ;
  wire addsub4_Madd_s_inst_lut2_39;
  wire \p_6_OBUF/XORF ;
  wire \p_6_OBUF/CYMUXG ;
  wire \p_6_OBUF/XORG ;
  wire addsub4_Madd_s_inst_lut2_40;
  wire addsub4_Madd_s_inst_cy_36;
  wire \p_6_OBUF/CYINIT ;
  wire addsub4_Madd_s_inst_lut2_41;
  wire \p_8_OBUF/XORF ;
  wire \p_8_OBUF/CYMUXG ;
  wire \p_8_OBUF/XORG ;
  wire addsub4_Madd_s_inst_lut2_42;
  wire addsub4_Madd_s_inst_cy_38;
  wire \p_8_OBUF/CYINIT ;
  wire addsub4_Madd_s_inst_lut2_43;
  wire \p_10_OBUF/XORF ;
  wire \p_10_OBUF/CYMUXG ;
  wire \p_10_OBUF/XORG ;
  wire addsub4_Madd_s_inst_lut2_44;
  wire addsub4_Madd_s_inst_cy_40;
  wire \p_10_OBUF/CYINIT ;
  wire addsub4_Madd_s_inst_lut2_45;
  wire \p_12_OBUF/XORF ;
  wire \p_12_OBUF/CYMUXG ;
  wire \p_12_OBUF/XORG ;
  wire addsub4_Madd_s_inst_lut2_46;
  wire addsub4_Madd_s_inst_cy_42;
  wire \p_12_OBUF/CYINIT ;
  wire \y1<0>/FROM ;
  wire \y1<0>/CYMUXG ;
  wire \y1<0>/XORG ;
  wire \y1<0>/GROM ;
  wire addsub1_Madd_s_inst_cy_0;
  wire \y1<0>/LOGIC_ZERO ;
  wire \addsub1_y_xor[2] ;
  wire \p1<2>/XORF ;
  wire \p1<2>/CYMUXG ;
  wire \p1<2>/LOGIC_ZERO ;
  wire \p1<2>/XORG ;
  wire \addsub1_y_xor[3] ;
  wire addsub1_Madd_s_inst_cy_2;
  wire \p1<2>/CYINIT ;
  wire \addsub1_y_xor[4] ;
  wire \p1<4>/XORF ;
  wire \p1<4>/CYMUXG ;
  wire \p1<4>/LOGIC_ZERO ;
  wire \p1<4>/XORG ;
  wire \addsub1_y_xor[5] ;
  wire addsub1_Madd_s_inst_cy_4;
  wire \p1<4>/CYINIT ;
  wire \addsub1_y_xor[6] ;
  wire \p1<6>/XORF ;
  wire \p1<6>/CYMUXG ;
  wire \p1<6>/LOGIC_ZERO ;
  wire \p1<6>/XORG ;
  wire \addsub1_y_xor[7] ;
  wire addsub1_Madd_s_inst_cy_6;
  wire \p1<6>/CYINIT ;
  wire N3275;
  wire \p1<8>/XORF ;
  wire \p1<8>/CYMUXG ;
  wire \p1<8>/LOGIC_ZERO ;
  wire \p1<8>/XORG ;
  wire N3279;
  wire addsub1_Madd_s_inst_cy_8;
  wire \p1<8>/CYINIT ;
  wire N3269;
  wire \p1<10>/XORF ;
  wire \p1<10>/CYMUXG ;
  wire \p1<10>/LOGIC_ZERO ;
  wire \p1<10>/XORG ;
  wire N3277;
  wire addsub1_Madd_s_inst_cy_10;
  wire \p1<10>/CYINIT ;
  wire N3273;
  wire \p1<12>/XORF ;
  wire \p1<12>/CYMUXG ;
  wire \p1<12>/LOGIC_ZERO ;
  wire \p1<12>/XORG ;
  wire N3271;
  wire addsub1_Madd_s_inst_cy_12;
  wire \p1<12>/CYINIT ;
  wire \addsub1_y_xor[14] ;
  wire \p1<14>/XORF ;
  wire \p1<14>/GROM ;
  wire \p1<14>/CYINIT ;
  wire \sel3<0>/FROM ;
  wire \sel3<0>/GROM ;
  wire \op3/FROM ;
  wire \op3/GROM ;
  wire \sel2<1>/FROM ;
  wire \sel2<1>/GROM ;
  wire \y2<3>/FROM ;
  wire \y2<3>/GROM ;
  wire \y3<1>/FROM ;
  wire \y3<1>/GROM ;
  wire \y2<5>/FROM ;
  wire \y2<5>/GROM ;
  wire \y4<4>/FROM ;
  wire \y4<4>/GROM ;
  wire addsub4_Madd_s_inst_lut2_47;
  wire \p_14_OBUF/XORF ;
  wire \p_14_OBUF/GROM ;
  wire \p_14_OBUF/CYINIT ;
  wire \y2<7>/FROM ;
  wire \y2<7>/GROM ;
  wire \y4<6>/FROM ;
  wire \y4<6>/GROM ;
  wire \y3<7>/FROM ;
  wire \y3<7>/GROM ;
  wire \sel2<0>/FROM ;
  wire \sel2<0>/GROM ;
  wire \addsub3_y_xor<0>/FROM ;
  wire \addsub3_y_xor<0>/GROM ;
  wire \sel4<0>/FROM ;
  wire \sel4<0>/GROM ;
  wire \op4/FROM ;
  wire \op4/GROM ;
  wire \addsub4_y_xor<0>/GROM ;
  wire addsub2_Madd_s_inst_lut2_27;
  wire \p2<12>/XORF ;
  wire \p2<12>/GROM ;
  wire \p2<12>/CYINIT ;
  wire \y3<4>/FROM ;
  wire \y3<4>/GROM ;
  wire \y3<6>/FROM ;
  wire \y3<6>/GROM ;
  wire addsub3_Madd_s_inst_lut2_38;
  wire \p3<10>/XORF ;
  wire \p3<10>/GROM ;
  wire \p3<10>/CYINIT ;
  wire \p<10>/ENABLE ;
  wire \p<10>/TORGTS ;
  wire \p<10>/OUTMUX ;
  wire \p<11>/ENABLE ;
  wire \p<11>/TORGTS ;
  wire \p<11>/OUTMUX ;
  wire \p<12>/ENABLE ;
  wire \p<12>/TORGTS ;
  wire \p<12>/OUTMUX ;
  wire \p<13>/ENABLE ;
  wire \p<13>/TORGTS ;
  wire \p<13>/OUTMUX ;
  wire \p<14>/ENABLE ;
  wire \p<14>/TORGTS ;
  wire \p<14>/OUTMUX ;
  wire \x<0>/IBUF ;
  wire \x<1>/IBUF ;
  wire \x<2>/IBUF ;
  wire \x<3>/IBUF ;
  wire \y<0>/IBUF ;
  wire \x<4>/IBUF ;
  wire \y<1>/IBUF ;
  wire \x<5>/IBUF ;
  wire \PWR_GND_0/GROM ;
  wire VCC;
  wire [0 : 0] y1;
  wire [12 : 2] p2;
  wire [7 : 1] y3;
  wire [10 : 2] p3;
  wire [14 : 2] p1;
  wire [7 : 1] y2;
  wire [0 : 0] addsub4_y_xor;
  wire [7 : 1] y4;
  wire [1 : 0] sel3;
  wire [1 : 0] sel2;
  wire [1 : 0] sel4;
  initial $sdf_annotate("booth_mult_timesim.sdf");
  X_IPAD \y<2>/PAD  (
    .PAD(y[2])
  );
  X_BUF \y<2>/IMUX  (
    .I(\y<2>/IBUF ),
    .O(y_2_IBUF)
  );
  X_BUF y_2_IBUF_0 (
    .I(y[2]),
    .O(\y<2>/IBUF )
  );
  X_IPAD \x<6>/PAD  (
    .PAD(x[6])
  );
  X_BUF \x<6>/IMUX  (
    .I(\x<6>/IBUF ),
    .O(x_6_IBUF)
  );
  X_BUF x_6_IBUF_1 (
    .I(x[6]),
    .O(\x<6>/IBUF )
  );
  X_IPAD \y<3>/PAD  (
    .PAD(y[3])
  );
  X_BUF \y<3>/IMUX  (
    .I(\y<3>/IBUF ),
    .O(y_3_IBUF)
  );
  X_BUF y_3_IBUF_2 (
    .I(y[3]),
    .O(\y<3>/IBUF )
  );
  X_IPAD \x<7>/PAD  (
    .PAD(x[7])
  );
  X_BUF \x<7>/IMUX  (
    .I(\x<7>/IBUF ),
    .O(x_7_IBUF)
  );
  X_BUF x_7_IBUF_3 (
    .I(x[7]),
    .O(\x<7>/IBUF )
  );
  X_IPAD \y<4>/PAD  (
    .PAD(y[4])
  );
  X_BUF \y<4>/IMUX  (
    .I(\y<4>/IBUF ),
    .O(y_4_IBUF)
  );
  X_BUF y_4_IBUF_4 (
    .I(y[4]),
    .O(\y<4>/IBUF )
  );
  X_IPAD \y<5>/PAD  (
    .PAD(y[5])
  );
  X_BUF \y<5>/IMUX  (
    .I(\y<5>/IBUF ),
    .O(y_5_IBUF)
  );
  X_BUF y_5_IBUF_5 (
    .I(y[5]),
    .O(\y<5>/IBUF )
  );
  X_IPAD \y<6>/PAD  (
    .PAD(y[6])
  );
  X_BUF \y<6>/IMUX  (
    .I(\y<6>/IBUF ),
    .O(y_6_IBUF)
  );
  X_BUF y_6_IBUF_6 (
    .I(y[6]),
    .O(\y<6>/IBUF )
  );
  X_IPAD \y<7>/PAD  (
    .PAD(y[7])
  );
  X_BUF \y<7>/IMUX  (
    .I(\y<7>/IBUF ),
    .O(y_7_IBUF)
  );
  X_BUF y_7_IBUF_7 (
    .I(y[7]),
    .O(\y<7>/IBUF )
  );
  X_OPAD \p<0>/PAD  (
    .PAD(p[0])
  );
  X_TRI p_0_OBUF (
    .I(\p<0>/OUTMUX ),
    .CTL(\p<0>/ENABLE ),
    .O(p[0])
  );
  X_INV \p<0>/ENABLEINV  (
    .I(\p<0>/TORGTS ),
    .O(\p<0>/ENABLE )
  );
  X_BUF \p<0>/GTS_OR  (
    .I(GTS),
    .O(\p<0>/TORGTS )
  );
  X_BUF \p<0>/OUTMUX_8  (
    .I(y1[0]),
    .O(\p<0>/OUTMUX )
  );
  X_OPAD \p<1>/PAD  (
    .PAD(p[1])
  );
  X_TRI p_1_OBUF_9 (
    .I(\p<1>/OUTMUX ),
    .CTL(\p<1>/ENABLE ),
    .O(p[1])
  );
  X_INV \p<1>/ENABLEINV  (
    .I(\p<1>/TORGTS ),
    .O(\p<1>/ENABLE )
  );
  X_BUF \p<1>/GTS_OR  (
    .I(GTS),
    .O(\p<1>/TORGTS )
  );
  X_BUF \p<1>/OUTMUX_10  (
    .I(p_1_OBUF),
    .O(\p<1>/OUTMUX )
  );
  X_OPAD \p<2>/PAD  (
    .PAD(p[2])
  );
  X_TRI p_2_OBUF_11 (
    .I(\p<2>/OUTMUX ),
    .CTL(\p<2>/ENABLE ),
    .O(p[2])
  );
  X_INV \p<2>/ENABLEINV  (
    .I(\p<2>/TORGTS ),
    .O(\p<2>/ENABLE )
  );
  X_BUF \p<2>/GTS_OR  (
    .I(GTS),
    .O(\p<2>/TORGTS )
  );
  X_BUF \p<2>/OUTMUX_12  (
    .I(p_2_OBUF),
    .O(\p<2>/OUTMUX )
  );
  X_OPAD \p<3>/PAD  (
    .PAD(p[3])
  );
  X_TRI p_3_OBUF_13 (
    .I(\p<3>/OUTMUX ),
    .CTL(\p<3>/ENABLE ),
    .O(p[3])
  );
  X_INV \p<3>/ENABLEINV  (
    .I(\p<3>/TORGTS ),
    .O(\p<3>/ENABLE )
  );
  X_BUF \p<3>/GTS_OR  (
    .I(GTS),
    .O(\p<3>/TORGTS )
  );
  X_BUF \p<3>/OUTMUX_14  (
    .I(p_3_OBUF),
    .O(\p<3>/OUTMUX )
  );
  X_OPAD \p<4>/PAD  (
    .PAD(p[4])
  );
  X_TRI p_4_OBUF_15 (
    .I(\p<4>/OUTMUX ),
    .CTL(\p<4>/ENABLE ),
    .O(p[4])
  );
  X_INV \p<4>/ENABLEINV  (
    .I(\p<4>/TORGTS ),
    .O(\p<4>/ENABLE )
  );
  X_BUF \p<4>/GTS_OR  (
    .I(GTS),
    .O(\p<4>/TORGTS )
  );
  X_BUF \p<4>/OUTMUX_16  (
    .I(p_4_OBUF),
    .O(\p<4>/OUTMUX )
  );
  X_OPAD \p<5>/PAD  (
    .PAD(p[5])
  );
  X_TRI p_5_OBUF_17 (
    .I(\p<5>/OUTMUX ),
    .CTL(\p<5>/ENABLE ),
    .O(p[5])
  );
  X_INV \p<5>/ENABLEINV  (
    .I(\p<5>/TORGTS ),
    .O(\p<5>/ENABLE )
  );
  X_BUF \p<5>/GTS_OR  (
    .I(GTS),
    .O(\p<5>/TORGTS )
  );
  X_BUF \p<5>/OUTMUX_18  (
    .I(p_5_OBUF),
    .O(\p<5>/OUTMUX )
  );
  X_OPAD \p<6>/PAD  (
    .PAD(p[6])
  );
  X_TRI p_6_OBUF_19 (
    .I(\p<6>/OUTMUX ),
    .CTL(\p<6>/ENABLE ),
    .O(p[6])
  );
  X_INV \p<6>/ENABLEINV  (
    .I(\p<6>/TORGTS ),
    .O(\p<6>/ENABLE )
  );
  X_BUF \p<6>/GTS_OR  (
    .I(GTS),
    .O(\p<6>/TORGTS )
  );
  X_BUF \p<6>/OUTMUX_20  (
    .I(p_6_OBUF),
    .O(\p<6>/OUTMUX )
  );
  X_OPAD \p<7>/PAD  (
    .PAD(p[7])
  );
  X_TRI p_7_OBUF_21 (
    .I(\p<7>/OUTMUX ),
    .CTL(\p<7>/ENABLE ),
    .O(p[7])
  );
  X_INV \p<7>/ENABLEINV  (
    .I(\p<7>/TORGTS ),
    .O(\p<7>/ENABLE )
  );
  X_BUF \p<7>/GTS_OR  (
    .I(GTS),
    .O(\p<7>/TORGTS )
  );
  X_BUF \p<7>/OUTMUX_22  (
    .I(p_7_OBUF),
    .O(\p<7>/OUTMUX )
  );
  X_OPAD \p<8>/PAD  (
    .PAD(p[8])
  );
  X_TRI p_8_OBUF_23 (
    .I(\p<8>/OUTMUX ),
    .CTL(\p<8>/ENABLE ),
    .O(p[8])
  );
  X_INV \p<8>/ENABLEINV  (
    .I(\p<8>/TORGTS ),
    .O(\p<8>/ENABLE )
  );
  X_BUF \p<8>/GTS_OR  (
    .I(GTS),
    .O(\p<8>/TORGTS )
  );
  X_BUF \p<8>/OUTMUX_24  (
    .I(p_8_OBUF),
    .O(\p<8>/OUTMUX )
  );
  X_OPAD \p<9>/PAD  (
    .PAD(p[9])
  );
  X_TRI p_9_OBUF_25 (
    .I(\p<9>/OUTMUX ),
    .CTL(\p<9>/ENABLE ),
    .O(p[9])
  );
  X_INV \p<9>/ENABLEINV  (
    .I(\p<9>/TORGTS ),