addsub3.v

来自「64位乘法器源码verilog,经过验证测试」· Verilog 代码 · 共 23 行

module addsub3(p,y,cin,op_y,op_c,s,cout);
    input [8:0] p;
    input [8:0] y;
    input cin;
    input op_y;
    input op_c;
    output [8:0] s;
    output cout;

	 wire [8:0] op_y_ext = {op_y, op_y, op_y, op_y, op_y, op_y, op_y, op_y};
	 wire [8:0] y_xor = op_y_ext ^ y;
	 wire [8:0] sum1;
	 wire c1;

	 assign {c1, sum1} = p + y_xor + op_y;
	 
	 wire cin_xor = cin ^ op_c;
	 wire [9:0] cin_xor_ext = {op_c, op_c, op_c, op_c, op_c, op_c, op_c, op_c, cin_xor};
	 
	 assign {cout, s} = {c1, sum1} + cin_xor_ext + op_c; 

endmodule