booth_mult.v

64位乘法器源码verilog,经过验证测试

module booth_mult(x,y,p);
    input [7:0] x;
    input [7:0] y;
    output [14:0] p;


	 wire [14:0] p0 = 15'b0;
	 wire [14:0] p1;
	 wire [12:0] p2;
	 wire [10:0] p3;
	 wire [8:0] p4;

	 wire op1, op2, op3, op4;
	 wire [1:0] sel1, sel2, sel3, sel4;

	 wire [8:0] y1, y2, y3, y4;

	 wire [2:0] x1 = x[1:0]<<1;

// computing y*x[1:0]
   boothcode code1(.x(x1), .op(op1), .sel(sel1));
	y_mux mux1(.y(y), .sel(sel1), .o(y1));
	addsub_c_15 addsub1(.p(p0), .y(y1), .op(op1), .s(p1));

// computing y*x[3:1]
	boothcode code2(.x(x[3:1]), .op(op2), .sel(sel2));
	y_mux mux2(.y(y), .sel(sel2), .o(y2));
	addsub_c_13 addsub2(.p(p1[14:2]), .y(y2), .op(op2), .s(p2));

// computing y*x[5:3]
   boothcode code3(.x(x[5:3]), .op(op3), .sel(sel3));
	y_mux mux3(.y(y), .sel(sel3), .o(y3));
	addsub_c_11 addsub3(.p(p2[12:2]), .y(y3), .op(op3), .s(p3));

// computing y*x[7:5]
	boothcode code4(.x(x[7:5]), .op(op4), .sel(sel4));
	y_mux mux4(.y(y), .sel(sel4), .o(y4));
	addsub_c_9 addsub4(.p(p3[10:2]), .y(y4), .op(op4), .s(p4));

	assign p = {p4[8:0], p3[1:0], p2[1:0], p1[1:0]}; 
endmodule