bw_mult_timesim.v

64位乘法器源码verilog,经过验证测试

// Xilinx Verilog netlist produced by netgen application (version G.31a)
// Command      : -intstyle ise -s 6 -pcf bw_mult.pcf -ngm bw_mult.ngm -w -ofmt verilog -sim bw_mult.ncd bw_mult_timesim.v 
// Input file   : bw_mult.ncd
// Output file  : bw_mult_timesim.v
// Design name  : bw_mult
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : 2s50tq144-6 (PRODUCTION 1.27 2003-12-13)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module bw_mult (
p, y, x
);
  output [14 : 0] p;
  input [7 : 0] y;
  input [7 : 0] x;
  wire p_10_OBUF;
  wire p_11_OBUF;
  wire p_12_OBUF;
  wire p_13_OBUF;
  wire p_14_OBUF;
  wire x_0_IBUF;
  wire x_1_IBUF;
  wire x_2_IBUF;
  wire x_3_IBUF;
  wire y_0_IBUF;
  wire x_4_IBUF;
  wire y_1_IBUF;
  wire x_5_IBUF;
  wire y_2_IBUF;
  wire x_6_IBUF;
  wire y_3_IBUF;
  wire x_7_IBUF;
  wire y_4_IBUF;
  wire y_5_IBUF;
  wire y_6_IBUF;
  wire y_7_IBUF;
  wire Mmult_p1_inst_lut2_0;
  wire p_1_OBUF;
  wire Mmult_p1_inst_lut2_6;
  wire p_3_OBUF;
  wire Mmult_p1_inst_lut2_15;
  wire p_5_OBUF;
  wire p_6_OBUF;
  wire p_7_OBUF;
  wire p_8_OBUF;
  wire p_9_OBUF;
  wire Mmult_p1_inst_cy_1;
  wire Mmult_p1_inst_cy_3;
  wire Mmult_p1_N142;
  wire Mmult_p1_N147;
  wire Mmult_p1_inst_cy_5;
  wire Mmult_p1_N152;
  wire Mmult_p1_N157;
  wire Mmult_p1_inst_cy_6;
  wire Mmult_p1_N162;
  wire Mmult_p1_N166;
  wire Mmult_p1_inst_cy_7;
  wire Madd__n0000_inst_cy_57;
  wire Madd__n0000_inst_lut2_33;
  wire Madd__n0000_inst_cy_59;
  wire Madd__n0000_inst_cy_61;
  wire Mmult_p1_inst_cy_9;
  wire Mmult_p1_N176;
  wire Mmult_p1_inst_cy_11;
  wire Mmult_p1_N181;
  wire Mmult_p1_N186;
  wire Mmult_p1_inst_cy_13;
  wire Mmult_p1_N191;
  wire Mmult_p1_N196;
  wire Mmult_p1_inst_cy_14;
  wire Mmult_p1_N201;
  wire Mmult_p1_inst_lut2_13;
  wire Mmult_p1_inst_cy_15;
  wire Mmult_p1_inst_cy_17;
  wire Mmult_p1_N215;
  wire Mmult_p1_inst_cy_19;
  wire Mmult_p1_N220;
  wire Mmult_p1_N225;
  wire Mmult_p1_inst_cy_21;
  wire Mmult_p1_N230;
  wire Mmult_p1_N235;
  wire Mmult_p1_inst_cy_22;
  wire Mmult_p1_N240;
  wire Mmult_p1_N244;
  wire Mmult_p1_inst_cy_23;
  wire Mmult_p1_inst_cy_25;
  wire Mmult_p1_N253;
  wire Mmult_p1_inst_cy_27;
  wire Mmult_p1_N257;
  wire Mmult_p1_N261;
  wire Mmult_p1_inst_cy_29;
  wire Mmult_p1_N265;
  wire Mmult_p1_inst_lut2_22;
  wire Mmult_p1_inst_lut2_23;
  wire Mmult_p1_inst_lut2_24;
  wire Mmult_p1_inst_cy_32;
  wire Mmult_p1_inst_cy_34;
  wire Mmult_p1_N278;
  wire Mmult_p1_N279;
  wire Mmult_p1_inst_cy_36;
  wire Mmult_p1_N280;
  wire Mmult_p1_N281;
  wire Mmult_p1_inst_cy_38;
  wire GLOBAL_LOGIC0;
  wire Mmult_p1_N282;
  wire Mmult_p1_N283;
  wire Mmult_p1_N284;
  wire Mmult_p1_inst_cy_40;
  wire Mmult_p1_inst_cy_42;
  wire Mmult_p1_inst_cy_44;
  wire Mmult_p1_inst_cy_46;
  wire Msub_d_inst_cy_49;
  wire Msub_d_inst_cy_51;
  wire Msub_d_inst_cy_53;
  wire GLOBAL_LOGIC0_0;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \p<10>/ENABLE ;
  wire \p<10>/TORGTS ;
  wire \p<10>/OUTMUX ;
  wire \p<11>/ENABLE ;
  wire \p<11>/TORGTS ;
  wire \p<11>/OUTMUX ;
  wire \p<12>/ENABLE ;
  wire \p<12>/TORGTS ;
  wire \p<12>/OUTMUX ;
  wire \p<13>/ENABLE ;
  wire \p<13>/TORGTS ;
  wire \p<13>/OUTMUX ;
  wire \p<14>/ENABLE ;
  wire \p<14>/TORGTS ;
  wire \p<14>/OUTMUX ;
  wire \x<0>/IBUF ;
  wire \x<1>/IBUF ;
  wire \x<2>/IBUF ;
  wire \x<3>/IBUF ;
  wire \y<0>/IBUF ;
  wire \x<4>/IBUF ;
  wire \y<1>/IBUF ;
  wire \x<5>/IBUF ;
  wire \y<2>/IBUF ;
  wire \x<6>/IBUF ;
  wire \y<3>/IBUF ;
  wire \x<7>/IBUF ;
  wire \y<4>/IBUF ;
  wire \y<5>/IBUF ;
  wire \y<6>/IBUF ;
  wire \y<7>/IBUF ;
  wire \p<0>/ENABLE ;
  wire \p<0>/TORGTS ;
  wire \p<0>/OUTMUX ;
  wire \p<1>/ENABLE ;
  wire \p<1>/TORGTS ;
  wire \p<1>/OUTMUX ;
  wire \p<2>/ENABLE ;
  wire \p<2>/TORGTS ;
  wire \p<2>/OUTMUX ;
  wire \p<3>/ENABLE ;
  wire \p<3>/TORGTS ;
  wire \p<3>/OUTMUX ;
  wire \p<4>/ENABLE ;
  wire \p<4>/TORGTS ;
  wire \p<4>/OUTMUX ;
  wire \p<5>/ENABLE ;
  wire \p<5>/TORGTS ;
  wire \p<5>/OUTMUX ;
  wire \p<6>/ENABLE ;
  wire \p<6>/TORGTS ;
  wire \p<6>/OUTMUX ;
  wire \p<7>/ENABLE ;
  wire \p<7>/TORGTS ;
  wire \p<7>/OUTMUX ;
  wire \p<8>/ENABLE ;
  wire \p<8>/TORGTS ;
  wire \p<8>/OUTMUX ;
  wire \p<9>/ENABLE ;
  wire \p<9>/TORGTS ;
  wire \p<9>/OUTMUX ;
  wire Mmult_p1_inst_multand_0;
  wire \Mmult_p1_inst_lut2_0/FROM ;
  wire \Mmult_p1_inst_lut2_0/CYMUXG ;
  wire Mmult_p1_inst_multand_1;
  wire \Mmult_p1_inst_lut2_0/XORG ;
  wire Mmult_p1_inst_lut4_0;
  wire Mmult_p1_inst_cy_0;
  wire \Mmult_p1_inst_lut2_0/LOGIC_ZERO ;
  wire Mmult_p1_inst_multand_2;
  wire Mmult_p1_inst_lut4_1;
  wire \Mmult_p1_N142/XORF ;
  wire \Mmult_p1_N142/CYMUXG ;
  wire Mmult_p1_inst_multand_3;
  wire \Mmult_p1_N142/XORG ;
  wire Mmult_p1_inst_lut4_2;
  wire Mmult_p1_inst_cy_2;
  wire \Mmult_p1_N142/CYINIT ;
  wire Mmult_p1_inst_multand_4;
  wire Mmult_p1_inst_lut4_3;
  wire \Mmult_p1_N152/XORF ;
  wire \Mmult_p1_N152/CYMUXG ;
  wire Mmult_p1_inst_multand_5;
  wire \Mmult_p1_N152/XORG ;
  wire Mmult_p1_inst_lut4_4;
  wire Mmult_p1_inst_cy_4;
  wire \Mmult_p1_N152/CYINIT ;
  wire Mmult_p1_inst_multand_6;
  wire Mmult_p1_inst_lut4_5;
  wire \Mmult_p1_N162/XORF ;
  wire \Mmult_p1_N162/CYMUXG ;
  wire \Mmult_p1_N162/LOGIC_ONE ;
  wire Mmult_p1_inst_cy_6_rt;
  wire \Mmult_p1_N162/CYINIT ;
  wire \Mmult_p1_N166/LOGIC_ZERO ;
  wire Mmult_p1_inst_lut2_1;
  wire \Mmult_p1_N166/CYMUXF ;
  wire \Mmult_p1_N166/XORF ;
  wire \Mmult_p1_N166/CYINIT ;
  wire \Madd__n0000_inst_lut2_33/FROM ;
  wire \Madd__n0000_inst_lut2_33/CYMUXG ;
  wire \Madd__n0000_inst_lut2_33/XORG ;
  wire Madd__n0000_inst_lut2_34;
  wire Madd__n0000_inst_cy_56;
  wire \Madd__n0000_inst_lut2_33/LOGIC_ZERO ;
  wire Madd__n0000_inst_lut2_35;
  wire \m<2>/XORF ;
  wire \m<2>/CYMUXG ;
  wire \m<2>/XORG ;
  wire Madd__n0000_inst_lut2_36;
  wire Madd__n0000_inst_cy_58;
  wire \m<2>/CYINIT ;
  wire Madd__n0000_inst_lut2_37;
  wire \m<4>/XORF ;
  wire \m<4>/CYMUXG ;
  wire \m<4>/XORG ;
  wire Madd__n0000_inst_lut2_38;
  wire Madd__n0000_inst_cy_60;
  wire \m<4>/CYINIT ;
  wire Madd__n0000_inst_lut2_39;
  wire \m<6>/CYMUXF ;
  wire \m<6>/XORF ;
  wire \m<6>/CYINIT ;
  wire Mmult_p1_inst_multand_7;
  wire Mmult_p1_inst_lut2_2;
  wire \Mmult_p1_N176/CYMUXG ;
  wire Mmult_p1_inst_multand_8;
  wire \Mmult_p1_N176/XORG ;
  wire Mmult_p1_inst_lut4_6;
  wire Mmult_p1_inst_cy_8;
  wire \Mmult_p1_N176/LOGIC_ZERO ;
  wire Mmult_p1_inst_multand_9;
  wire Mmult_p1_inst_lut4_7;
  wire \Mmult_p1_N181/XORF ;
  wire \Mmult_p1_N181/CYMUXG ;
  wire Mmult_p1_inst_multand_10;
  wire \Mmult_p1_N181/XORG ;
  wire Mmult_p1_inst_lut4_8;
  wire Mmult_p1_inst_cy_10;
  wire \Mmult_p1_N181/CYINIT ;
  wire Mmult_p1_inst_multand_11;
  wire Mmult_p1_inst_lut4_9;
  wire \Mmult_p1_N191/XORF ;
  wire \Mmult_p1_N191/CYMUXG ;
  wire Mmult_p1_inst_multand_12;
  wire \Mmult_p1_N191/XORG ;
  wire Mmult_p1_inst_lut4_10;
  wire Mmult_p1_inst_cy_12;
  wire \Mmult_p1_N191/CYINIT ;
  wire Mmult_p1_inst_multand_13;
  wire Mmult_p1_inst_lut4_11;
  wire \Mmult_p1_N201/XORF ;
  wire \Mmult_p1_N201/CYMUXG ;
  wire \Mmult_p1_N201/LOGIC_ONE ;
  wire Mmult_p1_inst_cy_14_rt;
  wire \Mmult_p1_N201/CYINIT ;
  wire \Mmult_p1_inst_lut2_13/LOGIC_ZERO ;
  wire Mmult_p1_inst_lut2_3;
  wire \Mmult_p1_inst_lut2_13/CYMUXF ;
  wire \Mmult_p1_inst_lut2_13/XORF ;
  wire \Mmult_p1_inst_lut2_13/CYINIT ;
  wire Mmult_p1_inst_multand_14;
  wire Mmult_p1_inst_lut2_4;
  wire \Mmult_p1_N215/CYMUXG ;
  wire Mmult_p1_inst_multand_15;
  wire \Mmult_p1_N215/XORG ;
  wire Mmult_p1_inst_lut4_12;
  wire Mmult_p1_inst_cy_16;
  wire \Mmult_p1_N215/LOGIC_ZERO ;
  wire Mmult_p1_inst_multand_16;
  wire Mmult_p1_inst_lut4_13;
  wire \Mmult_p1_N220/XORF ;
  wire \Mmult_p1_N220/CYMUXG ;
  wire Mmult_p1_inst_multand_17;
  wire \Mmult_p1_N220/XORG ;
  wire Mmult_p1_inst_lut4_14;
  wire Mmult_p1_inst_cy_18;
  wire \Mmult_p1_N220/CYINIT ;
  wire Mmult_p1_inst_multand_18;
  wire Mmult_p1_inst_lut4_15;
  wire \Mmult_p1_N230/XORF ;
  wire \Mmult_p1_N230/CYMUXG ;
  wire Mmult_p1_inst_multand_19;
  wire \Mmult_p1_N230/XORG ;
  wire Mmult_p1_inst_lut4_16;
  wire Mmult_p1_inst_cy_20;
  wire \Mmult_p1_N230/CYINIT ;
  wire Mmult_p1_inst_multand_20;
  wire Mmult_p1_inst_lut4_17;
  wire \Mmult_p1_N240/XORF ;
  wire \Mmult_p1_N240/CYMUXG ;
  wire \Mmult_p1_N240/LOGIC_ONE ;
  wire Mmult_p1_inst_cy_22_rt;
  wire \Mmult_p1_N240/CYINIT ;
  wire \Mmult_p1_N244/LOGIC_ZERO ;
  wire Mmult_p1_inst_lut2_5;
  wire \Mmult_p1_N244/CYMUXF ;
  wire \Mmult_p1_N244/XORF ;
  wire \Mmult_p1_N244/CYINIT ;
  wire Mmult_p1_inst_lut3_0;
  wire \Mmult_p1_N253/CYMUXG ;
  wire \Mmult_p1_N253/XORG ;
  wire Mmult_p1_inst_lut3_1;
  wire Mmult_p1_inst_cy_24;
  wire \Mmult_p1_N253/LOGIC_ZERO ;
  wire Mmult_p1_inst_lut3_2;
  wire \Mmult_p1_N257/XORF ;
  wire \Mmult_p1_N257/CYMUXG ;
  wire \Mmult_p1_N257/XORG ;
  wire Mmult_p1_inst_lut3_3;
  wire Mmult_p1_inst_cy_26;
  wire \Mmult_p1_N257/CYINIT ;
  wire Mmult_p1_inst_lut3_4;
  wire \Mmult_p1_N265/XORF ;
  wire \Mmult_p1_N265/CYMUXG ;
  wire \Mmult_p1_N265/XORG ;
  wire Mmult_p1_inst_lut3_5;
  wire Mmult_p1_inst_cy_28;
  wire \Mmult_p1_N265/CYINIT ;
  wire Mmult_p1_inst_lut3_6;
  wire \Mmult_p1_inst_lut2_23/CYMUXF ;
  wire \Mmult_p1_inst_lut2_23/XORF ;
  wire \Mmult_p1_inst_lut2_23/CYINIT ;
  wire \Mmult_p1_inst_lut2_6/FROM ;
  wire \Mmult_p1_inst_lut2_6/CYMUXG ;
  wire \Mmult_p1_inst_lut2_6/XORG ;
  wire Mmult_p1_inst_lut2_7;
  wire Mmult_p1_inst_cy_31;
  wire \Mmult_p1_inst_lut2_6/LOGIC_ZERO ;
  wire Mmult_p1_inst_lut2_8;
  wire \Mmult_p1_N278/XORF ;
  wire \Mmult_p1_N278/CYMUXG ;
  wire \Mmult_p1_N278/XORG ;
  wire Mmult_p1_inst_lut2_9;
  wire Mmult_p1_inst_cy_33;
  wire \Mmult_p1_N278/CYINIT ;
  wire Mmult_p1_inst_lut2_10;
  wire \Mmult_p1_N280/XORF ;
  wire \Mmult_p1_N280/CYMUXG ;
  wire \Mmult_p1_N280/XORG ;
  wire Mmult_p1_inst_lut2_11;
  wire Mmult_p1_inst_cy_35;
  wire \Mmult_p1_N280/CYINIT ;
  wire Mmult_p1_inst_lut2_12;
  wire \Mmult_p1_N282/XORF ;
  wire \Mmult_p1_N282/CYMUXG ;
  wire \Mmult_p1_N282/XORG ;
  wire \Mmult_p1_N282/GROM ;
  wire Mmult_p1_inst_cy_37;
  wire \Mmult_p1_N282/CYINIT ;
  wire Mmult_p1_inst_cy_15_rt;
  wire \Mmult_p1_N284/XORF ;
  wire \Mmult_p1_N284/CYINIT ;
  wire \Mmult_p1_inst_lut2_15/FROM ;
  wire \Mmult_p1_inst_lut2_15/CYMUXG ;
  wire \Mmult_p1_inst_lut2_15/XORG ;
  wire Mmult_p1_inst_lut2_16;
  wire Mmult_p1_inst_cy_39;
  wire \Mmult_p1_inst_lut2_15/LOGIC_ZERO ;
  wire Mmult_p1_inst_lut2_17;
  wire \p_6_OBUF/XORF ;
  wire \p_6_OBUF/CYMUXG ;
  wire \p_6_OBUF/XORG ;
  wire Mmult_p1_inst_lut2_18;
  wire Mmult_p1_inst_cy_41;
  wire \p_6_OBUF/CYINIT ;
  wire Mmult_p1_inst_lut2_19;
  wire \p2<8>/XORF ;
  wire \p2<8>/CYMUXG ;
  wire \p2<8>/XORG ;
  wire Mmult_p1_inst_lut2_20;
  wire Mmult_p1_inst_cy_43;
  wire \p2<8>/CYINIT ;
  wire Mmult_p1_inst_lut2_21;
  wire \p2<10>/XORF ;
  wire \p2<10>/CYMUXG ;
  wire \p2<10>/XORG ;
  wire \p2<10>/GROM ;
  wire Mmult_p1_inst_cy_45;
  wire \p2<10>/CYINIT ;
  wire \p2<12>/LOGIC_ZERO ;
  wire \p2<12>/FROM ;
  wire \p2<12>/XORF ;
  wire \p2<12>/XORG ;
  wire Mmult_p1_inst_lut2_24_rt;
  wire Mmult_p1_inst_cy_47;
  wire \p2<12>/CYINIT ;
  wire Msub_d_inst_lut2_25;
  wire \p_7_OBUF/XORF ;
  wire \p_7_OBUF/CYMUXG ;
  wire \p_7_OBUF/XORG ;
  wire Msub_d_inst_lut2_26;
  wire Msub_d_inst_cy_48;
  wire \p_7_OBUF/CYINIT ;
  wire \p_7_OBUF/LOGIC_ONE ;
  wire Msub_d_inst_lut2_27;
  wire \p_9_OBUF/XORF ;
  wire \p_9_OBUF/CYMUXG ;
  wire \p_9_OBUF/XORG ;
  wire Msub_d_inst_lut2_28;
  wire Msub_d_inst_cy_50;
  wire \p_9_OBUF/CYINIT ;
  wire Msub_d_inst_lut2_29;
  wire \p_11_OBUF/XORF ;
  wire \p_11_OBUF/CYMUXG ;
  wire \p_11_OBUF/XORG ;
  wire Msub_d_inst_lut2_30;
  wire Msub_d_inst_cy_52;
  wire \p_11_OBUF/CYINIT ;
  wire Msub_d_inst_lut2_31;
  wire \p_13_OBUF/XORF ;
  wire \p_13_OBUF/XORG ;
  wire Msub_d_inst_lut2_32;
  wire Msub_d_inst_cy_54;
  wire \p_13_OBUF/CYINIT ;
  wire \PWR_GND_0/GROM ;
  wire \PWR_GND_1/GROM ;
  wire VCC;
  wire NLW_Mmult_p1_inst_cy_6_rt_IA_UNCONNECTED;
  wire NLW_Mmult_p1_inst_cy_14_rt_IA_UNCONNECTED;
  wire NLW_Mmult_p1_inst_cy_22_rt_IA_UNCONNECTED;
  wire [7 : 1] m;
  wire [13 : 7] p2;
  wire [6 : 0] y7x;
  initial $sdf_annotate("bw_mult_timesim.sdf");
  X_OPAD \p<10>/PAD  (
    .PAD(p[10])
  );
  X_TRI p_10_OBUF_0 (
    .I(\p<10>/OUTMUX ),
    .CTL(\p<10>/ENABLE ),
    .O(p[10])
  );
  X_INV \p<10>/ENABLEINV  (
    .I(\p<10>/TORGTS ),
    .O(\p<10>/ENABLE )
  );
  X_BUF \p<10>/GTS_OR  (
    .I(GTS),
    .O(\p<10>/TORGTS )
  );
  X_BUF \p<10>/OUTMUX_1  (
    .I(p_10_OBUF),
    .O(\p<10>/OUTMUX )
  );
  X_OPAD \p<11>/PAD  (
    .PAD(p[11])
  );
  X_TRI p_11_OBUF_2 (
    .I(\p<11>/OUTMUX ),
    .CTL(\p<11>/ENABLE ),
    .O(p[11])
  );
  X_INV \p<11>/ENABLEINV  (
    .I(\p<11>/TORGTS ),
    .O(\p<11>/ENABLE )
  );
  X_BUF \p<11>/GTS_OR  (
    .I(GTS),
    .O(\p<11>/TORGTS )
  );
  X_BUF \p<11>/OUTMUX_3  (
    .I(p_11_OBUF),
    .O(\p<11>/OUTMUX )
  );
  X_OPAD \p<12>/PAD  (
    .PAD(p[12])
  );
  X_TRI p_12_OBUF_4 (
    .I(\p<12>/OUTMUX ),
    .CTL(\p<12>/ENABLE ),
    .O(p[12])
  );
  X_INV \p<12>/ENABLEINV  (
    .I(\p<12>/TORGTS ),
    .O(\p<12>/ENABLE )
  );
  X_BUF \p<12>/GTS_OR  (
    .I(GTS),
    .O(\p<12>/TORGTS )
  );
  X_BUF \p<12>/OUTMUX_5  (
    .I(p_12_OBUF),
    .O(\p<12>/OUTMUX )
  );
  X_OPAD \p<13>/PAD  (
    .PAD(p[13])
  );
  X_TRI p_13_OBUF_6 (
    .I(\p<13>/OUTMUX ),
    .CTL(\p<13>/ENABLE ),
    .O(p[13])
  );
  X_INV \p<13>/ENABLEINV  (
    .I(\p<13>/TORGTS ),
    .O(\p<13>/ENABLE )
  );
  X_BUF \p<13>/GTS_OR  (
    .I(GTS),
    .O(\p<13>/TORGTS )
  );
  X_BUF \p<13>/OUTMUX_7  (
    .I(p_13_OBUF),
    .O(\p<13>/OUTMUX )
  );
  X_OPAD \p<14>/PAD  (
    .PAD(p[14])
  );
  X_TRI p_14_OBUF_8 (
    .I(\p<14>/OUTMUX ),
    .CTL(\p<14>/ENABLE ),
    .O(p[14])
  );
  X_INV \p<14>/ENABLEINV  (
    .I(\p<14>/TORGTS ),
    .O(\p<14>/ENABLE )
  );
  X_BUF \p<14>/GTS_OR  (
    .I(GTS),
    .O(\p<14>/TORGTS )
  );
  X_BUF \p<14>/OUTMUX_9  (
    .I(p_14_OBUF),
    .O(\p<14>/OUTMUX )
  );