wallace_timesim.v

64位乘法器源码verilog,经过验证测试

// Xilinx Verilog netlist produced by netgen application (version G.31a)
// Command      : -intstyle ise -s 6 -pcf wallace.pcf -ngm wallace.ngm -w -ofmt verilog -sim wallace.ncd wallace_timesim.v 
// Input file   : wallace.ncd
// Output file  : wallace_timesim.v
// Design name  : wallace
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : 2s50tq144-6 (PRODUCTION 1.27 2003-12-13)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module wallace (
p, y, x
);
  output [15 : 0] p;
  input [7 : 0] y;
  input [7 : 0] x;
  wire p_8_OBUF;
  wire p_9_OBUF;
  wire Madd__n0000_inst_cy_5;
  wire Madd__n0000_inst_lut2_4;
  wire Madd__n0000_inst_lut2_5;
  wire p_6_OBUF;
  wire Madd__n0000_inst_cy_7;
  wire \sss0[6] ;
  wire Madd__n0000_inst_lut2_7;
  wire p_7_OBUF;
  wire Madd__n0000_inst_cy_9;
  wire \sss0[8] ;
  wire \sss0[9] ;
  wire p_10_OBUF;
  wire Madd__n0000_inst_cy_11;
  wire \sss0[10] ;
  wire \sss0[11] ;
  wire p_11_OBUF;
  wire p_12_OBUF;
  wire Madd__n0000_inst_cy_13;
  wire \sss0[12] ;
  wire p_13_OBUF;
  wire p_14_OBUF;
  wire x_7_IBUF;
  wire y_7_IBUF;
  wire x_6_IBUF;
  wire y_6_IBUF;
  wire p_15_OBUF;
  wire x_3_IBUF;
  wire x_0_IBUF;
  wire \p3[6] ;
  wire \p0[6] ;
  wire y_2_IBUF;
  wire x_5_IBUF;
  wire \p6[2] ;
  wire \p5[2] ;
  wire \sss0[5] ;
  wire N3257;
  wire y_0_IBUF;
  wire x_2_IBUF;
  wire \p5[0] ;
  wire x_1_IBUF;
  wire \p0[7] ;
  wire y_3_IBUF;
  wire \p3[3] ;
  wire \p5[3] ;
  wire \p6[3] ;
  wire \p0[4] ;
  wire y_4_IBUF;
  wire N3279;
  wire x_4_IBUF;
  wire \p5[7] ;
  wire y_1_IBUF;
  wire \p5[1] ;
  wire N3314;
  wire \p5[4] ;
  wire N3267;
  wire y_5_IBUF;
  wire \p3[5] ;
  wire \p5[5] ;
  wire N3284;
  wire \p3[4] ;
  wire \p3[0] ;
  wire \sss0[7] ;
  wire \p6[0] ;
  wire N3293;
  wire \p6[1] ;
  wire \p6[7] ;
  wire \p0[0] ;
  wire N3263;
  wire N3318;
  wire \p3[7] ;
  wire \sss0[3] ;
  wire \p6[4] ;
  wire N3271;
  wire N3301;
  wire \p6[5] ;
  wire N3288;
  wire \p3[2] ;
  wire N3297;
  wire \p0[2] ;
  wire N3305;
  wire N3310;
  wire N3275;
  wire \p0[3] ;
  wire \p0[5] ;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \p<8>/ENABLE ;
  wire \p<8>/TORGTS ;
  wire \p<8>/OUTMUX ;
  wire \p<9>/ENABLE ;
  wire \p<9>/TORGTS ;
  wire \p<9>/OUTMUX ;
  wire Madd__n0000_inst_lut2_4_rt;
  wire \p_6_OBUF/CYMUXG ;
  wire \p_6_OBUF/XORG ;
  wire \p_6_OBUF/GROM ;
  wire Madd__n0000_inst_cy_4;
  wire \p_6_OBUF/LOGIC_ZERO ;
  wire Madd__n0000_inst_lut2_6;
  wire \p_7_OBUF/XORF ;
  wire \p_7_OBUF/CYMUXG ;
  wire \p_7_OBUF/XORG ;
  wire \p_7_OBUF/GROM ;
  wire Madd__n0000_inst_cy_6;
  wire \p_7_OBUF/CYINIT ;
  wire Madd__n0000_inst_lut2_8;
  wire \p_9_OBUF/XORF ;
  wire \p_9_OBUF/CYMUXG ;
  wire \p_9_OBUF/XORG ;
  wire Madd__n0000_inst_lut2_9;
  wire Madd__n0000_inst_cy_8;
  wire \p_9_OBUF/CYINIT ;
  wire Madd__n0000_inst_lut2_10;
  wire \p_11_OBUF/XORF ;
  wire \p_11_OBUF/CYMUXG ;
  wire \p_11_OBUF/XORG ;
  wire Madd__n0000_inst_lut2_11;
  wire Madd__n0000_inst_cy_10;
  wire \p_11_OBUF/CYINIT ;
  wire Madd__n0000_inst_lut2_12;
  wire \p_13_OBUF/XORF ;
  wire \p_13_OBUF/CYMUXG ;
  wire \p_13_OBUF/XORG ;
  wire Madd__n0000_inst_lut2_13;
  wire Madd__n0000_inst_cy_12;
  wire \p_13_OBUF/CYINIT ;
  wire \p_15_OBUF/XORF ;
  wire \p_15_OBUF/GROM ;
  wire \p_15_OBUF/CYINIT ;
  wire \p3<6>/FROM ;
  wire \p3<6>/GROM ;
  wire \p6<2>/FROM ;
  wire \p6<2>/GROM ;
  wire \p7<2>/FROM ;
  wire \p7<2>/GROM ;
  wire \Madd__n0000_inst_lut2_4/FROM ;
  wire \Madd__n0000_inst_lut2_4/GROM ;
  wire \p5<0>/FROM ;
  wire \p5<0>/GROM ;
  wire \p0<7>/FROM ;
  wire \p0<7>/GROM ;
  wire \p7<6>/FROM ;
  wire \p7<6>/GROM ;
  wire \p3<3>/FROM ;
  wire \p3<3>/GROM ;
  wire \p6<3>/FROM ;
  wire \p6<3>/GROM ;
  wire \c0<4>/FROM ;
  wire \c0<4>/GROM ;
  wire \N3279/FROM ;
  wire \N3279/GROM ;
  wire \p5<7>/FROM ;
  wire \p5<7>/GROM ;
  wire \p5<1>/FROM ;
  wire \p5<1>/GROM ;
  wire \N3314/FROM ;
  wire \N3314/GROM ;
  wire \p2<3>/FROM ;
  wire \p2<3>/GROM ;
  wire \N3267/FROM ;
  wire \N3267/GROM ;
  wire \p3<5>/FROM ;
  wire \p3<5>/GROM ;
  wire \c0<6>/FROM ;
  wire \c0<6>/GROM ;
  wire \N3284/FROM ;
  wire \N3284/GROM ;
  wire \c1<4>/FROM ;
  wire \c1<4>/GROM ;
  wire \ccc0<5>/FROM ;
  wire \ccc0<5>/GROM ;
  wire \p3<4>/FROM ;
  wire \p3<4>/GROM ;
  wire \p3<0>/FROM ;
  wire \p3<0>/GROM ;
  wire \ccc0<6>/FROM ;
  wire \ccc0<6>/GROM ;
  wire \ccc0<10>/FROM ;
  wire \ccc0<10>/GROM ;
  wire \s0<1>/FROM ;
  wire \s0<1>/GROM ;
  wire \s0<8>/FROM ;
  wire \s0<8>/GROM ;
  wire \s1<9>/FROM ;
  wire \s1<9>/GROM ;
  wire \p7<5>/FROM ;
  wire \p7<5>/GROM ;
  wire \p6<1>/FROM ;
  wire \p6<1>/GROM ;
  wire \ccc0<7>/FROM ;
  wire \ccc0<7>/GROM ;
  wire \ccc0<8>/FROM ;
  wire \ccc0<8>/GROM ;
  wire \ccc0<12>/FROM ;
  wire \ccc0<12>/GROM ;
  wire \sss0<10>/GROM ;
  wire \ssss0<6>/FROM ;
  wire \ssss0<6>/GROM ;
  wire \p0<0>/FROM ;
  wire \p0<0>/GROM ;
  wire \p7<4>/FROM ;
  wire \p7<4>/GROM ;
  wire \ccc0<9>/FROM ;
  wire \ccc0<9>/GROM ;
  wire \N3263/FROM ;
  wire \N3263/GROM ;
  wire \ss0<5>/GROM ;
  wire \ss0<4>/GROM ;
  wire \N3318/FROM ;
  wire \N3318/GROM ;
  wire \c1<6>/FROM ;
  wire \c1<6>/GROM ;
  wire \ss0<6>/GROM ;
  wire \c1<7>/FROM ;
  wire \c1<7>/GROM ;
  wire \p3<7>/FROM ;
  wire \p3<7>/GROM ;
  wire \c1<8>/FROM ;
  wire \c1<8>/GROM ;
  wire \cc0<2>/FROM ;
  wire \cc0<2>/GROM ;
  wire \c1<9>/FROM ;
  wire \c1<9>/GROM ;
  wire \N3293/FROM ;
  wire \N3293/GROM ;
  wire \cc0<3>/FROM ;
  wire \cc0<3>/GROM ;
  wire \N3271/FROM ;
  wire \N3271/GROM ;
  wire \ss1<6>/FROM ;
  wire \ss1<6>/GROM ;
  wire \ss0<8>/GROM ;
  wire \N3301/FROM ;
  wire \N3301/GROM ;
  wire \cc0<4>/FROM ;
  wire \cc0<4>/GROM ;
  wire \c1<10>/FROM ;
  wire \c1<10>/GROM ;
  wire \N3288/FROM ;
  wire \N3288/GROM ;
  wire \c1<11>/FROM ;
  wire \c1<11>/GROM ;
  wire \ssss0<5>/GROM ;
  wire \p6<7>/FROM ;
  wire \p6<7>/GROM ;
  wire \cc0<6>/FROM ;
  wire \cc0<6>/GROM ;
  wire \p6<4>/FROM ;
  wire \p6<4>/GROM ;
  wire \cc0<7>/FROM ;
  wire \cc0<7>/GROM ;
  wire \p6<5>/FROM ;
  wire \p6<5>/GROM ;
  wire \p3<2>/FROM ;
  wire \p3<2>/GROM ;
  wire \cc0<8>/FROM ;
  wire \cc0<8>/GROM ;
  wire \N3297/FROM ;
  wire \N3297/GROM ;
  wire \p0<2>/FROM ;
  wire \p0<2>/GROM ;
  wire \N3305/FROM ;
  wire \N3305/GROM ;
  wire \N3310/FROM ;
  wire \N3310/GROM ;
  wire \N3275/FROM ;
  wire \N3275/GROM ;
  wire \p0<3>/FROM ;
  wire \p0<3>/GROM ;
  wire \ssss0<12>/GROM ;
  wire \p0<4>/GROM ;
  wire \ss1<11>/FROM ;
  wire \ss1<11>/GROM ;
  wire \c0<1>/FROM ;
  wire \c0<1>/GROM ;
  wire \p0<5>/FROM ;
  wire \p0<5>/GROM ;
  wire \cc1<7>/GROM ;
  wire \p<10>/ENABLE ;
  wire \p<10>/TORGTS ;
  wire \p<10>/OUTMUX ;
  wire \p<11>/ENABLE ;
  wire \p<11>/TORGTS ;
  wire \p<11>/OUTMUX ;
  wire \p<12>/ENABLE ;
  wire \p<12>/TORGTS ;
  wire \p<12>/OUTMUX ;
  wire \p<13>/ENABLE ;
  wire \p<13>/TORGTS ;
  wire \p<13>/OUTMUX ;
  wire \p<14>/ENABLE ;
  wire \p<14>/TORGTS ;
  wire \p<14>/OUTMUX ;
  wire \p<15>/ENABLE ;
  wire \p<15>/TORGTS ;
  wire \p<15>/OUTMUX ;
  wire \x<0>/IBUF ;
  wire \x<1>/IBUF ;
  wire \x<2>/IBUF ;
  wire \x<3>/IBUF ;
  wire \x<4>/IBUF ;
  wire \y<0>/IBUF ;
  wire \y<1>/IBUF ;
  wire \x<5>/IBUF ;
  wire \y<2>/IBUF ;
  wire \x<6>/IBUF ;
  wire \x<7>/IBUF ;
  wire \y<3>/IBUF ;
  wire \y<4>/IBUF ;
  wire \y<5>/IBUF ;
  wire \y<6>/IBUF ;
  wire \y<7>/IBUF ;
  wire \p<0>/ENABLE ;
  wire \p<0>/TORGTS ;
  wire \p<0>/OUTMUX ;
  wire \p<1>/ENABLE ;
  wire \p<1>/TORGTS ;
  wire \p<1>/OUTMUX ;
  wire \p<2>/ENABLE ;
  wire \p<2>/TORGTS ;
  wire \p<2>/OUTMUX ;
  wire \p<3>/ENABLE ;
  wire \p<3>/TORGTS ;
  wire \p<3>/OUTMUX ;
  wire \p<4>/ENABLE ;
  wire \p<4>/TORGTS ;
  wire \p<4>/OUTMUX ;
  wire \p<5>/ENABLE ;
  wire \p<5>/TORGTS ;
  wire \p<5>/OUTMUX ;
  wire \p<6>/ENABLE ;
  wire \p<6>/TORGTS ;
  wire \p<6>/OUTMUX ;
  wire \p<7>/ENABLE ;
  wire \p<7>/TORGTS ;
  wire \p<7>/OUTMUX ;
  wire VCC;
  wire [14 : 4] ssss0;
  wire [12 : 4] ccc0;
  wire [12 : 7] cc1;
  wire [13 : 6] ss1;
  wire [6 : 0] p7;
  wire [11 : 4] c1;
  wire [9 : 2] ss0;
  wire [9 : 2] cc0;
  wire [5 : 0] p2;
  wire [8 : 1] c0;
  wire [11 : 4] s1;
  wire [8 : 1] s0;
  wire [14 : 14] cccc0;
  initial $sdf_annotate("wallace_timesim.sdf");
  X_OPAD \p<8>/PAD  (
    .PAD(p[8])
  );
  X_TRI p_8_OBUF_0 (
    .I(\p<8>/OUTMUX ),
    .CTL(\p<8>/ENABLE ),
    .O(p[8])
  );
  X_INV \p<8>/ENABLEINV  (
    .I(\p<8>/TORGTS ),
    .O(\p<8>/ENABLE )
  );
  X_BUF \p<8>/GTS_OR  (
    .I(GTS),
    .O(\p<8>/TORGTS )
  );
  X_BUF \p<8>/OUTMUX_1  (
    .I(p_8_OBUF),
    .O(\p<8>/OUTMUX )
  );
  X_OPAD \p<9>/PAD  (
    .PAD(p[9])
  );
  X_TRI p_9_OBUF_2 (
    .I(\p<9>/OUTMUX ),
    .CTL(\p<9>/ENABLE ),
    .O(p[9])
  );
  X_INV \p<9>/ENABLEINV  (
    .I(\p<9>/TORGTS ),
    .O(\p<9>/ENABLE )
  );
  X_BUF \p<9>/GTS_OR  (
    .I(GTS),
    .O(\p<9>/TORGTS )
  );
  X_BUF \p<9>/OUTMUX_3  (
    .I(p_9_OBUF),
    .O(\p<9>/OUTMUX )
  );
  X_ZERO \p_6_OBUF/LOGIC_ZERO_4  (
    .O(\p_6_OBUF/LOGIC_ZERO )
  );
  X_MUX2 Madd__n0000_inst_cy_4_5 (
    .IA(ssss0[5]),
    .IB(\p_6_OBUF/LOGIC_ZERO ),
    .SEL(Madd__n0000_inst_lut2_4_rt),
    .O(Madd__n0000_inst_cy_4)
  );
  defparam Madd__n0000_inst_lut2_4_rt_6.INIT = 16'hFF00;
  X_LUT4 Madd__n0000_inst_lut2_4_rt_6 (
    .ADR0(ssss0[5]),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(Madd__n0000_inst_lut2_4),
    .O(Madd__n0000_inst_lut2_4_rt)
  );
  defparam \p_6_OBUF/G .INIT = 16'hF0F0;
  X_LUT4 \p_6_OBUF/G  (
    .ADR0(ssss0[6]),
    .ADR1(VCC),
    .ADR2(Madd__n0000_inst_lut2_5),
    .ADR3(VCC),
    .O(\p_6_OBUF/GROM )
  );
  X_BUF \p_6_OBUF/COUTUSED  (
    .I(\p_6_OBUF/CYMUXG ),
    .O(Madd__n0000_inst_cy_5)
  );
  X_BUF \p_6_OBUF/YUSED  (
    .I(\p_6_OBUF/XORG ),
    .O(p_6_OBUF)
  );
  X_MUX2 Madd__n0000_inst_cy_5_7 (
    .IA(ssss0[6]),
    .IB(Madd__n0000_inst_cy_4),
    .SEL(\p_6_OBUF/GROM ),
    .O(\p_6_OBUF/CYMUXG )
  );
  X_XOR2 Madd__n0000_inst_sum_5 (
    .I0(Madd__n0000_inst_cy_4),
    .I1(\p_6_OBUF/GROM ),
    .O(\p_6_OBUF/XORG )
  );
  X_MUX2 Madd__n0000_inst_cy_6_8 (
    .IA(ssss0[7]),
    .IB(\p_7_OBUF/CYINIT ),
    .SEL(Madd__n0000_inst_lut2_6),
    .O(Madd__n0000_inst_cy_6)
  );
  X_XOR2 Madd__n0000_inst_sum_6 (
    .I0(\p_7_OBUF/CYINIT ),
    .I1(Madd__n0000_inst_lut2_6),
    .O(\p_7_OBUF/XORF )
  );
  defparam Madd__n0000_inst_lut2_61.INIT = 16'h66AA;
  X_LUT4 Madd__n0000_inst_lut2_61 (
    .ADR0(ssss0[7]),
    .ADR1(\sss0[6] ),
    .ADR2(VCC),
    .ADR3(ccc0[5]),
    .O(Madd__n0000_inst_lut2_6)
  );
  defparam \p_7_OBUF/G .INIT = 16'hFF00;
  X_LUT4 \p_7_OBUF/G  (
    .ADR0(ssss0[8]),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(Madd__n0000_inst_lut2_7),
    .O(\p_7_OBUF/GROM )
  );
  X_BUF \p_7_OBUF/COUTUSED  (
    .I(\p_7_OBUF/CYMUXG ),
    .O(Madd__n0000_inst_cy_7)
  );
  X_BUF \p_7_OBUF/XUSED  (
    .I(\p_7_OBUF/XORF ),
    .O(p_7_OBUF)
  );
  X_BUF \p_7_OBUF/YUSED  (
    .I(\p_7_OBUF/XORG ),
    .O(p_8_OBUF)
  );
  X_MUX2 Madd__n0000_inst_cy_7_9 (
    .IA(ssss0[8]),
    .IB(Madd__n0000_inst_cy_6),
    .SEL(\p_7_OBUF/GROM ),
    .O(\p_7_OBUF/CYMUXG )
  );
  X_XOR2 Madd__n0000_inst_sum_7 (
    .I0(Madd__n0000_inst_cy_6),
    .I1(\p_7_OBUF/GROM ),
    .O(\p_7_OBUF/XORG )
  );
  X_BUF \p_7_OBUF/CYINIT_10  (
    .I(Madd__n0000_inst_cy_5),
    .O(\p_7_OBUF/CYINIT )
  );
  X_MUX2 Madd__n0000_inst_cy_8_11 (
    .IA(ssss0[9]),
    .IB(\p_9_OBUF/CYINIT ),
    .SEL(Madd__n0000_inst_lut2_8),
    .O(Madd__n0000_inst_cy_8)
  );
  X_XOR2 Madd__n0000_inst_sum_8 (
    .I0(\p_9_OBUF/CYINIT ),
    .I1(Madd__n0000_inst_lut2_8),
    .O(\p_9_OBUF/XORF )
  );
  defparam Madd__n0000_inst_lut2_81.INIT = 16'h566A;
  X_LUT4 Madd__n0000_inst_lut2_81 (
    .ADR0(ssss0[9]),
    .ADR1(ccc0[7]),
    .ADR2(\sss0[8] ),
    .ADR3(cc1[7]),
    .O(Madd__n0000_inst_lut2_8)
  );
  defparam Madd__n0000_inst_lut2_91.INIT = 16'h566A;
  X_LUT4 Madd__n0000_inst_lut2_91 (
    .ADR0(ssss0[10]),
    .ADR1(cc1[8]),
    .ADR2(ccc0[8]),
    .ADR3(\sss0[9] ),
    .O(Madd__n0000_inst_lut2_9)
  );
  X_BUF \p_9_OBUF/COUTUSED  (
    .I(\p_9_OBUF/CYMUXG ),
    .O(Madd__n0000_inst_cy_9)
  );
  X_BUF \p_9_OBUF/XUSED  (
    .I(\p_9_OBUF/XORF ),
    .O(p_9_OBUF)
  );
  X_BUF \p_9_OBUF/YUSED  (
    .I(\p_9_OBUF/XORG ),
    .O(p_10_OBUF)
  );
  X_MUX2 Madd__n0000_inst_cy_9_12 (
    .IA(ssss0[10]),
    .IB(Madd__n0000_inst_cy_8),
    .SEL(Madd__n0000_inst_lut2_9),
    .O(\p_9_OBUF/CYMUXG )
  );
  X_XOR2 Madd__n0000_inst_sum_9 (
    .I0(Madd__n0000_inst_cy_8),
    .I1(Madd__n0000_inst_lut2_9),
    .O(\p_9_OBUF/XORG )
  );
  X_BUF \p_9_OBUF/CYINIT_13  (
    .I(Madd__n0000_inst_cy_7),
    .O(\p_9_OBUF/CYINIT )
  );
  X_MUX2 Madd__n0000_inst_cy_10_14 (
    .IA(ssss0[11]),
    .IB(\p_11_OBUF/CYINIT ),
    .SEL(Madd__n0000_inst_lut2_10),
    .O(Madd__n0000_inst_cy_10)
  );
  X_XOR2 Madd__n0000_inst_sum_10 (
    .I0(\p_11_OBUF/CYINIT ),
    .I1(Madd__n0000_inst_lut2_10),
    .O(\p_11_OBUF/XORF )
  );
  defparam Madd__n0000_inst_lut2_101.INIT = 16'h566A;
  X_LUT4 Madd__n0000_inst_lut2_101 (
    .ADR0(ssss0[11]),
    .ADR1(\sss0[10] ),
    .ADR2(ccc0[9]),
    .ADR3(cc1[9]),
    .O(Madd__n0000_inst_lut2_10)
  );
  defparam Madd__n0000_inst_lut2_111.INIT = 16'h566A;
  X_LUT4 Madd__n0000_inst_lut2_111 (
    .ADR0(ssss0[12]),
    .ADR1(cc1[10]),
    .ADR2(\sss0[11] ),
    .ADR3(ccc0[10]),
    .O(Madd__n0000_inst_lut2_11)
  );
  X_BUF \p_11_OBUF/COUTUSED  (
    .I(\p_11_OBUF/CYMUXG ),
    .O(Madd__n0000_inst_cy_11)
  );
  X_BUF \p_11_OBUF/XUSED  (
    .I(\p_11_OBUF/XORF ),
    .O(p_11_OBUF)
  );
  X_BUF \p_11_OBUF/YUSED  (
    .I(\p_11_OBUF/XORG ),
    .O(p_12_OBUF)
  );
  X_MUX2 Madd__n0000_inst_cy_11_15 (
    .IA(ssss0[12]),
    .IB(Madd__n0000_inst_cy_10),
    .SEL(Madd__n0000_inst_lut2_11),
    .O(\p_11_OBUF/CYMUXG )
  );
  X_XOR2 Madd__n0000_inst_sum_11 (
    .I0(Madd__n0000_inst_cy_10),
    .I1(Madd__n0000_inst_lut2_11),
    .O(\p_11_OBUF/XORG )
  );
  X_BUF \p_11_OBUF/CYINIT_16  (
    .I(Madd__n0000_inst_cy_9),
    .O(\p_11_OBUF/CYINIT )
  );
  X_MUX2 Madd__n0000_inst_cy_12_17 (
    .IA(ssss0[13]),
    .IB(\p_13_OBUF/CYINIT ),
    .SEL(Madd__n0000_inst_lut2_12),
    .O(Madd__n0000_inst_cy_12)
  );
  X_XOR2 Madd__n0000_inst_sum_12 (
    .I0(\p_13_OBUF/CYINIT ),
    .I1(Madd__n0000_inst_lut2_12),
    .O(\p_13_OBUF/XORF )
  );
  defparam Madd__n0000_inst_lut2_121.INIT = 16'h566A;
  X_LUT4 Madd__n0000_inst_lut2_121 (
    .ADR0(ssss0[13]),
    .ADR1(ccc0[11]),
    .ADR2(cc1[11]),
    .ADR3(\sss0[12] ),
    .O(Madd__n0000_inst_lut2_12)
  );
  defparam Madd__n0000_inst_lut2_131.INIT = 16'h566A;
  X_LUT4 Madd__n0000_inst_lut2_131 (
    .ADR0(ssss0[14]),
    .ADR1(cc1[12]),
    .ADR2(ccc0[12]),
    .ADR3(ss1[13]),
    .O(Madd__n0000_inst_lut2_13)
  );
  X_BUF \p_13_OBUF/COUTUSED  (
    .I(\p_13_OBUF/CYMUXG ),
    .O(Madd__n0000_inst_cy_13)
  );
  X_BUF \p_13_OBUF/XUSED  (
    .I(\p_13_OBUF/XORF ),
    .O(p_13_OBUF)
  );
  X_BUF \p_13_OBUF/YUSED  (
    .I(\p_13_OBUF/XORG ),
    .O(p_14_OBUF)
  );
  X_MUX2 Madd__n0000_inst_cy_13_18 (
    .IA(ssss0[14]),
    .IB(Madd__n0000_inst_cy_12),
    .SEL(Madd__n0000_inst_lut2_13),
    .O(\p_13_OBUF/CYMUXG )
  );
  X_XOR2 Madd__n0000_inst_sum_13 (
    .I0(Madd__n0000_inst_cy_12),
    .I1(Madd__n0000_inst_lut2_13),
    .O(\p_13_OBUF/XORG )
  );
  X_BUF \p_13_OBUF/CYINIT_19  (
    .I(Madd__n0000_inst_cy_11),
    .O(\p_13_OBUF/CYINIT )
  );
  X_XOR2 Madd__n0000_inst_sum_14 (
    .I0(\p_15_OBUF/CYINIT ),
    .I1(cccc0[14]),
    .O(\p_15_OBUF/XORF )
  );
  defparam \csa5_co<14>1 .INIT = 16'h8000;
  X_LUT4 \csa5_co<14>1  (
    .ADR0(y_6_IBUF),
    .ADR1(x_7_IBUF),
    .ADR2(y_7_IBUF),
    .ADR3(x_6_IBUF),
    .O(cccc0[14])
  );
  defparam \csa3_Mxor_s_Xo<27>1 .INIT = 16'h7888;
  X_LUT4 \csa3_Mxor_s_Xo<27>1  (
    .ADR0(y_6_IBUF),
    .ADR1(x_7_IBUF),
    .ADR2(y_7_IBUF),
    .ADR3(x_6_IBUF),
    .O(\p_15_OBUF/GROM )
  );
  X_BUF \p_15_OBUF/XUSED  (
    .I(\p_15_OBUF/XORF ),
    .O(p_15_OBUF)
  );
  X_BUF \p_15_OBUF/YUSED  (
    .I(\p_15_OBUF/GROM ),
    .O(ss1[13])
  );
  X_BUF \p_15_OBUF/CYINIT_20  (
    .I(Madd__n0000_inst_cy_13),
    .O(\p_15_OBUF/CYINIT )
  );
  defparam \m3_p<6>1 .INIT = 16'hC0C0;
  X_LUT4 \m3_p<6>1  (
    .ADR0(VCC),
    .ADR1(y_6_IBUF),
    .ADR2(x_3_IBUF),
    .ADR3(VCC),
    .O(\p3<6>/FROM )
  );
  defparam \m0_p<6>1 .INIT = 16'hAA00;
  X_LUT4 \m0_p<6>1  (
    .ADR0(x_0_IBUF),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(y_6_IBUF),
    .O(\p3<6>/GROM )
  );
  X_BUF \p3<6>/XUSED  (
    .I(\p3<6>/FROM ),
    .O(\p3[6] )
  );
  X_BUF \p3<6>/YUSED  (
    .I(\p3<6>/GROM ),
    .O(\p0[6] )
  );
  defparam \m6_p<2>1 .INIT = 16'hAA00;
  X_LUT4 \m6_p<2>1  (
    .ADR0(x_6_IBUF),
    .ADR1(VCC),
    .ADR2(VCC),
    .ADR3(y_2_IBUF),
    .O(\p6<2>/FROM )