array_mult.v

64位乘法器源码verilog,经过验证测试

module array_mult(x,y,p);
    input [7:0] x;
    input [7:0] y;
    output [15:0] p;
    wire [6:0] row0, row1, row2, row3, row4, row5, row6, row7, c0, c1, c2, c3, c4, c5, c6, c7;

    /* generate first row of products */
	 // assign row0[7] = x[7] & y[0];
	 assign row0[6] = x[6] & y[0];
	 assign row0[5] = x[5] & y[0];
    assign row0[4] = x[4] & y[0];    
	 assign row0[3] = x[3] & y[0];
	 assign row0[2] = x[2] & y[0];
    assign row0[1] = x[1] & y[0];
    assign row0[0] = x[0] & y[0]; 
    assign p[0] = row0[0];
    assign c0 = 7'b0000000;
	 // synthesis attribute rloc of p0 is r0c0
    multrow p0(row0,x,y[1],y[0],c0,row1,c1);
    assign p[1] = row1[0];
	 multrow p1(row1,x,y[2],y[1],c1,row2,c2);
    assign p[2] = row2[0];
    multrow p2(row2,x,y[3],y[2],c2,row3,c3);
    assign p[3] = row3[0];
    multrow p3(row3,x,y[4],y[3],c3,row4,c4);
    assign p[4] = row4[0];
    multrow p4(row4,x,y[5],y[4],c4,row5,c5);
    assign p[5] = row5[0];
    multrow p5(row5,x,y[6],y[5],c5,row6,c6);
    assign p[6] = row6[0];
    multrow p7(row6,x,y[7],y[6],c6,row7,c7);
    assign p[7] = row7[0];
    lastrow l({x[7] & y[7],row7[6:1]},c7,p[14:8],p[15]);
endmodule