1pps_c.vhd

应用VHDL语言将高稳晶振分频得到1pps

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-- Company: 
-- Engineer:
--
-- Create Date:    16:11:22 09/09/07
-- Design Name:    
-- Module Name:    1PPS_C - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PPS_C is
  port(PPS_In : in std_logic;
           50MHz_In: in std_logic;
	         PPS_Out:out std_logic);
end PPS_C;

architecture Behavioral of PPS_C is
  signal PPS_Fine:std_logic;
	signal No_disturb:std_logic:='1';	
	 signal 50MHz_Out:std_logic;
	  signal GPS_syn:std_logic;
	   signal Pulse_Count;
		 signal 50MHz_Count:std_logic;
		 signal Warp_Count:std_logic;
	   signal 50MHz_CountOld:std_logic;
	 signal aver_cnt:std_logic;
	signal time_cnt:std_logic;
begin
	  process(PPS_Judge)
     begin
          if(PPS_In'event and PPS_In='1'and No_disturb='1')then
               PPS_Fine<='1';
	            PPS_Out<=1PPS_In;
	       end if;
	  end process;		 
	  process(50MHz_Judge)
	  begin
	       if(GPS_syn='1')then
	         if(PPS_Fine='1'and (Pulse_Count<50000010 and Pulse_Count>49999990))then
		          No_disturb<='0';
		           Pulse_Count<='0';
		      else
		           No_disturb<='1';
	              Pulse_Count<=Pulse_Count+1;
		      end if;
		    end if;
		  50MHz_Out<=50MHz_In;
		end process;
		process(PPS_Create)
		begin
		     if(GPS_syn='1')then
	        	 if(PPS_Fine='1'and time_cnt=10000)then
		         Warp_Count<=50MHz_Count-50MHz_CountOld;
			       50MHz_CountOld<=50MHz_Count;
			        time_cnt<='0';
			     else
				     time_cnt<=time_cnt+1;
			     elsif(50MHz_Count=50000000)
			         PPS_Out<='1';
                  time_cnt<=time_cnt+1;
                 50MHz_Count<='0';
                time_cnt<=time_cnt+1;
              PPS_Out<='0';
              elsif(time_cnt=10000)
                 50MHz_Count<=50MHz_Count+Warp_Count;
                 aver_cnt<=50MHz_Count/time_cnt;
              elsif(50MHz_Count'event and 50MHz_Count='1')
               50MHz_Count<=50MHz_Count+1;
              end if;
             end if;
        end process;
 component clk_500div 
   port(clk:in std_logic;
        clk_div500:out std_logic);
 end component clk_500div;
 component clk_10div 
   port(clk:in std_logic;
        clk_div10:out std_logic);
 end component clk_10div;
  component clk_5div 
   port(clk:in std_logic;
        clk_div5:out std_logic);
 end component clk_5div;
 signal clk_tmp1,clk_tmp2:std_logic;
begin
    U1:clk_5div
	    port map(clk,clk_tmp1);
	 U2:clk_10div
		 port map(clk_tmp1,clk_tmp2);
    U3:clk_100div
	    port map(clk_tmp2,clk_div500);
end Behavioral;