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Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/1PPS/clk_10div.vhd" in Library work.Architecture behavioral of Entity clk_10div is up to date.Compiling vhdl file "C:/1PPS/clk_5div.vhd" in Library work.Architecture behavioral of Entity clk_5div is up to date.Compiling vhdl file "C:/1PPS/clk_100div.vhd" in Library work.Architecture behavioral of Entity clk_100div is up to date.Compiling vhdl file "C:/1PPS/1PPS_C.vhd" in Library work.ERROR:HDLParsers:164 - "C:/1PPS/1PPS_C.vhd" Line 30. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER--> Total memory usage is 77060 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/1PPS/clk_10div.vhd" in Library work.Architecture behavioral of Entity clk_10div is up to date.Compiling vhdl file "C:/1PPS/clk_5div.vhd" in Library work.Architecture behavioral of Entity clk_5div is up to date.Compiling vhdl file "C:/1PPS/clk_100div.vhd" in Library work.Architecture behavioral of Entity clk_100div is up to date.Compiling vhdl file "C:/1PPS/1PPS_C.vhd" in Library work.ERROR:HDLParsers:164 - "C:/1PPS/1PPS_C.vhd" Line 30. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER--> Total memory usage is 77060 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/1PPS/clk_10div.vhd" in Library work.Architecture behavioral of Entity clk_10div is up to date.Compiling vhdl file "C:/1PPS/clk_5div.vhd" in Library work.Architecture behavioral of Entity clk_5div is up to date.Compiling vhdl file "C:/1PPS/clk_100div.vhd" in Library work.Architecture behavioral of Entity clk_100div is up to date.Compiling vhdl file "C:/1PPS/1PPS_C.vhd" in Library work.ERROR:HDLParsers:164 - "C:/1PPS/1PPS_C.vhd" Line 30. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER--> Total memory usage is 77060 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/1PPS/clk_10div.vhd" in Library work.Architecture behavioral of Entity clk_10div is up to date.Compiling vhdl file "C:/1PPS/clk_100div.vhd" in Library work.Architecture behavioral of Entity clk_100div is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <clk_100div> (Architecture <behavioral>).Entity <clk_100div> analyzed. Unit <clk_100div> generated.Analyzing Entity <clk_10div> (Architecture <behavioral>).Entity <clk_10div> analyzed. Unit <clk_10div> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clk_10div>. Related source file is "C:/1PPS/clk_10div.vhd". Found 1-bit register for signal <clk_tmp>. Found 3-bit up counter for signal <cnt>. Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s).Unit <clk_10div> synthesized.Synthesizing Unit <clk_100div>. Related source file is "C:/1PPS/clk_100div.vhd".Unit <clk_100div> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 2 3-bit up counter : 2# Registers : 2 1-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clk_100div> ...Optimizing unit <clk_10div> ...Loading device for application Rf_Device from file '3s50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clk_100div, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 5 out of 768 0% Number of Slice Flip Flops: 8 out of 1536 0% Number of 4 input LUTs: 6 out of 1536 0% Number of bonded IOBs: 2 out of 124 1% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+U1/clk_tmp:Q | NONE | 4 |clk | BUFGP | 4 |-----------------------------------+------------------------+-------+INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -5 Minimum period: 3.851ns (Maximum Frequency: 259.680MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 6.280ns Maximum combinational path delay: No path found=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd c:\1pps/_ngo -i -p xc3s50-pq208-5clk_100div.ngc clk_100div.ngd Reading NGO file 'C:/1PPS/clk_100div.ngc' ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "clk_100div.ngd" ...Writing NGDBUILD log file "clk_100div.bld"...NGDBUILD done.
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