fifo_cntl.v

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

//////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2008 www.aimlab.cn
//
// Design by huanghui
//
// File name : fifo_cntl.v
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
//
// This program is to test aimlab's CY7C68013+EPM1270 Slave Sysn FIFO
// System input clock 50MHZ
// Write Slave FIFO 25MHZ by divid input clock
//
// Tested  2008.07.14
////////////////////////////////////////////////////////////////////////////////////
module fifo_cntl(
				input empty,
				input [1:0] btn, 
				input full,
				input clk,
				output reg [15:0] o_data, 
				output [1:0] fifoadr, 
				output pktend,
				output reg slwr,
				output [2:0] led,
				output ifclk,
				output slcs);
				
parameter NUM=4096,IDLE=0,WORK=1,CH_NUM=8; 

reg clk_25M; 
reg [11:0] counter; 
reg state; 
reg [3:0] channel;

reg btn_a,btn_b; 
wire btn_c; 
reg [4:0] num; 

assign fifoadr = 2'b00;    //Select EP2 endpoint
assign pktend = 1'b1; 	   //Always invalid Zerolenth input
assign slcs = 1'b1;		//select slave fifo

assign led[2] = empty; 	   //LED will light when FIFO empty
assign led[1] = slwr;        //LED will light when CPLD is writting data to FIFO
assign led[0] = full;      //LED will light when FIFO Full

assign ifclk =~clk_25M;	   //Sysn clock to FX2

always@(posedge clk) 
	begin 
		if( num == 5'b00111 ) 
			begin 
				num <= 0; 
				clk_25M <= ~clk_25M; 
			end 
		else 
			num <= num+1;
	end 

always@(posedge clk_25M or negedge btn[0]) 
	if( !btn[0] ) 
		state <= IDLE; 
	else 
	begin 
		case(state) 
			IDLE: 
				begin 
					if(btn_c) 
						state <= WORK; 
					else 
						state <= IDLE; 
				end 
			WORK: 
				begin 
//					if( counter == 12'h3FF ) 
						state <= IDLE; 
				end 
		endcase 
	end 

always@(posedge clk_25M or negedge btn[0]) 
	if(!btn[0]) 
		begin 
			counter = 0; 
			slwr = 1; 
			o_data <= 16'haaaa; 
		end 
	else 
		begin 
			if(state == IDLE) 
				begin 
					slwr = 1; 
					o_data <= 16'hbbbb; 
				end 
			else 
				if( state == WORK ) 
					begin 
						if( !full ) 
							begin 
								slwr = 1; 
							end 
						else 
							begin 
								slwr = 0;
								o_data = {channel,counter};  
								if( counter == 12'h3FE ) 
									counter = 12'h000; 
								else 
									counter <= counter+1;
								
								if( channel == 4'b0111 ) 
									channel = 4'b0000;
								else
									channel = channel+1;
							end 
					end 
		end 

always@(posedge clk_25M or negedge btn[0]) 
	if( !btn[0] ) 
		begin 
			btn_a <= 0; 
			btn_b <= 0; 
		end 
	else 
		begin 
			btn_a <= !btn[1]; 
		end 

assign btn_c = btn_a;
 
endmodule