prev_cmp_fifo_cntl.map.qmsg

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 26 11:22:33 2008 " "Info: Processing started: Sat Jul 26 11:22:33 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fifo_cntl -c fifo_cntl " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo_cntl -c fifo_cntl" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fifo_cntl.v(85) " "Warning (10268): Verilog HDL information at fifo_cntl.v(85): Always Construct contains both blocking and non-blocking assignments" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 85 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "NUM num fifo_cntl.v(32) " "Info (10281): Verilog HDL Declaration information at fifo_cntl.v(32): object \"NUM\" differs only in case from object \"num\" in the same scope" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 32 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo_cntl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fifo_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_cntl " "Info: Found entity 1: fifo_cntl" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fifo_cntl " "Info: Elaborating entity \"fifo_cntl\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "btn_b fifo_cntl.v(39) " "Warning (10036): Verilog HDL or VHDL warning at fifo_cntl.v(39): object \"btn_b\" assigned a value but never read" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 39 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 fifo_cntl.v(61) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(61): truncated value with size 32 to match size of target (5)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(66) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(66): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(73) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(73): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(75) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(75): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(80) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(80): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 fifo_cntl.v(113) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(113): truncated value with size 32 to match size of target (12)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 fifo_cntl.v(118) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(118): truncated value with size 32 to match size of target (4)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "channel\[3\] data_in GND " "Warning (14130): Reduced register \"channel\[3\]\" with stuck data_in port to stuck value GND" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "fifoadr\[0\] GND " "Warning (13410): Pin \"fifoadr\[0\]\" stuck at GND" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 25 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "fifoadr\[1\] GND " "Warning (13410): Pin \"fifoadr\[1\]\" stuck at GND" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 25 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pktend VCC " "Warning (13410): Pin \"pktend\" stuck at VCC" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 26 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "slcs GND " "Warning (13410): Pin \"slcs\" stuck at GND" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 30 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 27 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "94 " "Info: Implemented 94 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "25 " "Info: Implemented 25 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.map.smsg " "Info: Generated suppressed messages file D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 26 11:22:38 2008 " "Info: Processing ended: Sat Jul 26 11:22:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}