fifo_cntl.map.qmsg

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus II " "Info: Running Quartus II Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 04 08:48:37 2008 " "Info: Processing started: Thu Sep 04 08:48:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fifo_cntl -c fifo_cntl --analysis_and_elaboration " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo_cntl -c fifo_cntl --analysis_and_elaboration" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fifo_cntl.v(85) " "Warning (10268): Verilog HDL information at fifo_cntl.v(85): always construct contains both blocking and non-blocking assignments" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 85 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "NUM num fifo_cntl.v(32) " "Info (10281): Verilog HDL Declaration information at fifo_cntl.v(32): object \"NUM\" differs only in case from object \"num\" in the same scope" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 32 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo_cntl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fifo_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_cntl " "Info: Found entity 1: fifo_cntl" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fifo_cntl " "Info: Elaborating entity \"fifo_cntl\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "btn_b fifo_cntl.v(39) " "Warning (10036): Verilog HDL or VHDL warning at fifo_cntl.v(39): object \"btn_b\" assigned a value but never read" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 39 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 fifo_cntl.v(61) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(61): truncated value with size 32 to match size of target (5)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(66) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(66): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(73) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(73): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(75) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(75): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 fifo_cntl.v(80) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(80): truncated value with size 32 to match size of target (1)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 fifo_cntl.v(113) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(113): truncated value with size 32 to match size of target (12)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 fifo_cntl.v(118) " "Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(118): truncated value with size 32 to match size of target (4)" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.map.smsg " "Info: Generated suppressed messages file D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 8 s Quartus II " "Info: Quartus II Analysis & Elaboration was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Info: Peak virtual memory: 151 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 04 08:48:48 2008 " "Info: Processing ended: Thu Sep 04 08:48:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}