prev_cmp_fifo_cntl.tan.qmsg

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

{ "Info" "ITDB_FULL_TPD_RESULT" "full led\[0\] 8.422 ns Longest " "Info: Longest tpd from source pin \"full\" to destination pin \"led\[0\]\" is 8.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns full 1 PIN PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 5; PIN Node = 'full'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { full } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.968 ns) + CELL(2.322 ns) 8.422 ns led\[0\] 2 PIN PIN_112 0 " "Info: 2: + IC(4.968 ns) + CELL(2.322 ns) = 8.422 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'led\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { full led[0] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 41.01 % ) " "Info: Total cell delay = 3.454 ns ( 41.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.968 ns ( 58.99 % ) " "Info: Total interconnect delay = 4.968 ns ( 58.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.422 ns" { full led[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.422 ns" { full {} full~combout {} led[0] {} } { 0.000ns 0.000ns 4.968ns } { 0.000ns 1.132ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "slwr~reg0 full clk 4.305 ns register " "Info: th for register \"slwr~reg0\" (data pin = \"full\", clock pin = \"clk\") is 4.305 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.588 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_20 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk_25M 2 REG LC_X10_Y4_N2 36 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 36; REG Node = 'clk_25M'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk_25M } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.475 ns) + CELL(0.918 ns) 9.588 ns slwr~reg0 3 REG LC_X11_Y7_N5 2 " "Info: 3: + IC(4.475 ns) + CELL(0.918 ns) = 9.588 ns; Loc. = LC_X11_Y7_N5; Fanout = 2; REG Node = 'slwr~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.393 ns" { clk_25M slwr~reg0 } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.20 % ) " "Info: Total cell delay = 3.375 ns ( 35.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.213 ns ( 64.80 % ) " "Info: Total interconnect delay = 6.213 ns ( 64.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M slwr~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} slwr~reg0 {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.504 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.504 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns full 1 PIN PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 5; PIN Node = 'full'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { full } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.781 ns) + CELL(0.591 ns) 5.504 ns slwr~reg0 2 REG LC_X11_Y7_N5 2 " "Info: 2: + IC(3.781 ns) + CELL(0.591 ns) = 5.504 ns; Loc. = LC_X11_Y7_N5; Fanout = 2; REG Node = 'slwr~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.372 ns" { full slwr~reg0 } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 31.30 % ) " "Info: Total cell delay = 1.723 ns ( 31.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.781 ns ( 68.70 % ) " "Info: Total interconnect delay = 3.781 ns ( 68.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.504 ns" { full slwr~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.504 ns" { full {} full~combout {} slwr~reg0 {} } { 0.000ns 0.000ns 3.781ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M slwr~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} slwr~reg0 {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.504 ns" { full slwr~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.504 ns" { full {} full~combout {} slwr~reg0 {} } { 0.000ns 0.000ns 3.781ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 26 11:22:55 2008 " "Info: Processing ended: Sat Jul 26 11:22:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}