prev_cmp_fifo_cntl.tan.qmsg

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 23 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_25M " "Info: Detected ripple clock \"clk_25M\" as buffer" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 34 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_25M" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[1\] register counter\[7\] 120.32 MHz 8.311 ns Internal " "Info: Clock \"clk\" has Internal fmax of 120.32 MHz between source register \"counter\[1\]\" and destination register \"counter\[7\]\" (period= 8.311 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.602 ns + Longest register register " "Info: + Longest register to register delay is 7.602 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[1\] 1 REG LC_X11_Y5_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y5_N2; Fanout = 5; REG Node = 'counter\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[1] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.468 ns) + CELL(0.914 ns) 3.382 ns Equal1~106 2 COMB LC_X6_Y4_N5 10 " "Info: 2: + IC(2.468 ns) + CELL(0.914 ns) = 3.382 ns; Loc. = LC_X6_Y4_N5; Fanout = 10; COMB Node = 'Equal1~106'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.382 ns" { counter[1] Equal1~106 } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.159 ns) + CELL(1.061 ns) 7.602 ns counter\[7\] 3 REG LC_X13_Y5_N9 5 " "Info: 3: + IC(3.159 ns) + CELL(1.061 ns) = 7.602 ns; Loc. = LC_X13_Y5_N9; Fanout = 5; REG Node = 'counter\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.220 ns" { Equal1~106 counter[7] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.975 ns ( 25.98 % ) " "Info: Total cell delay = 1.975 ns ( 25.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.627 ns ( 74.02 % ) " "Info: Total interconnect delay = 5.627 ns ( 74.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.602 ns" { counter[1] Equal1~106 counter[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.602 ns" { counter[1] {} Equal1~106 {} counter[7] {} } { 0.000ns 2.468ns 3.159ns } { 0.000ns 0.914ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.588 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_20 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk_25M 2 REG LC_X10_Y4_N2 36 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 36; REG Node = 'clk_25M'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk_25M } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.475 ns) + CELL(0.918 ns) 9.588 ns counter\[7\] 3 REG LC_X13_Y5_N9 5 " "Info: 3: + IC(4.475 ns) + CELL(0.918 ns) = 9.588 ns; Loc. = LC_X13_Y5_N9; Fanout = 5; REG Node = 'counter\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.393 ns" { clk_25M counter[7] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.20 % ) " "Info: Total cell delay = 3.375 ns ( 35.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.213 ns ( 64.80 % ) " "Info: Total interconnect delay = 6.213 ns ( 64.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M counter[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} counter[7] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.588 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_20 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk_25M 2 REG LC_X10_Y4_N2 36 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 36; REG Node = 'clk_25M'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk_25M } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.475 ns) + CELL(0.918 ns) 9.588 ns counter\[1\] 3 REG LC_X11_Y5_N2 5 " "Info: 3: + IC(4.475 ns) + CELL(0.918 ns) = 9.588 ns; Loc. = LC_X11_Y5_N2; Fanout = 5; REG Node = 'counter\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.393 ns" { clk_25M counter[1] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.20 % ) " "Info: Total cell delay = 3.375 ns ( 35.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.213 ns ( 64.80 % ) " "Info: Total interconnect delay = 6.213 ns ( 64.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M counter[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} counter[1] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M counter[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} counter[7] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M counter[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} counter[1] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.602 ns" { counter[1] Equal1~106 counter[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.602 ns" { counter[1] {} Equal1~106 {} counter[7] {} } { 0.000ns 2.468ns 3.159ns } { 0.000ns 0.914ns 1.061ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M counter[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} counter[7] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M counter[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} counter[1] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "channel\[0\] btn\[0\] clk -0.096 ns register " "Info: tsu for register \"channel\[0\]\" (data pin = \"btn\[0\]\", clock pin = \"clk\") is -0.096 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.159 ns + Longest pin register " "Info: + Longest pin to register delay is 9.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns btn\[0\] 1 PIN PIN_74 32 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_74; Fanout = 32; PIN Node = 'btn\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { btn[0] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.878 ns) + CELL(0.200 ns) 7.210 ns channel\[0\]~416 2 COMB LC_X11_Y7_N6 3 " "Info: 2: + IC(5.878 ns) + CELL(0.200 ns) = 7.210 ns; Loc. = LC_X11_Y7_N6; Fanout = 3; COMB Node = 'channel\[0\]~416'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.078 ns" { btn[0] channel[0]~416 } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(1.243 ns) 9.159 ns channel\[0\] 3 REG LC_X11_Y7_N2 4 " "Info: 3: + IC(0.706 ns) + CELL(1.243 ns) = 9.159 ns; Loc. = LC_X11_Y7_N2; Fanout = 4; REG Node = 'channel\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.949 ns" { channel[0]~416 channel[0] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.575 ns ( 28.11 % ) " "Info: Total cell delay = 2.575 ns ( 28.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.584 ns ( 71.89 % ) " "Info: Total interconnect delay = 6.584 ns ( 71.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.159 ns" { btn[0] channel[0]~416 channel[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.159 ns" { btn[0] {} btn[0]~combout {} channel[0]~416 {} channel[0] {} } { 0.000ns 0.000ns 5.878ns 0.706ns } { 0.000ns 1.132ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.588 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_20 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk_25M 2 REG LC_X10_Y4_N2 36 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 36; REG Node = 'clk_25M'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk_25M } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.475 ns) + CELL(0.918 ns) 9.588 ns channel\[0\] 3 REG LC_X11_Y7_N2 4 " "Info: 3: + IC(4.475 ns) + CELL(0.918 ns) = 9.588 ns; Loc. = LC_X11_Y7_N2; Fanout = 4; REG Node = 'channel\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.393 ns" { clk_25M channel[0] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.20 % ) " "Info: Total cell delay = 3.375 ns ( 35.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.213 ns ( 64.80 % ) " "Info: Total interconnect delay = 6.213 ns ( 64.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M channel[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} channel[0] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.159 ns" { btn[0] channel[0]~416 channel[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.159 ns" { btn[0] {} btn[0]~combout {} channel[0]~416 {} channel[0] {} } { 0.000ns 0.000ns 5.878ns 0.706ns } { 0.000ns 1.132ns 0.200ns 1.243ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M channel[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} channel[0] {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk o_data\[9\] o_data\[9\]~reg0 15.227 ns register " "Info: tco from clock \"clk\" to destination pin \"o_data\[9\]\" through register \"o_data\[9\]~reg0\" is 15.227 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.588 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_20 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk_25M 2 REG LC_X10_Y4_N2 36 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 36; REG Node = 'clk_25M'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk_25M } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.475 ns) + CELL(0.918 ns) 9.588 ns o_data\[9\]~reg0 3 REG LC_X7_Y10_N2 1 " "Info: 3: + IC(4.475 ns) + CELL(0.918 ns) = 9.588 ns; Loc. = LC_X7_Y10_N2; Fanout = 1; REG Node = 'o_data\[9\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.393 ns" { clk_25M o_data[9]~reg0 } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.20 % ) " "Info: Total cell delay = 3.375 ns ( 35.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.213 ns ( 64.80 % ) " "Info: Total interconnect delay = 6.213 ns ( 64.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M o_data[9]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} o_data[9]~reg0 {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.263 ns + Longest register pin " "Info: + Longest register to pin delay is 5.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns o_data\[9\]~reg0 1 REG LC_X7_Y10_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y10_N2; Fanout = 1; REG Node = 'o_data\[9\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { o_data[9]~reg0 } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.941 ns) + CELL(2.322 ns) 5.263 ns o_data\[9\] 2 PIN PIN_144 0 " "Info: 2: + IC(2.941 ns) + CELL(2.322 ns) = 5.263 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'o_data\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.263 ns" { o_data[9]~reg0 o_data[9] } "NODE_NAME" } } { "fifo_cntl.v" "" { Text "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 44.12 % ) " "Info: Total cell delay = 2.322 ns ( 44.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.941 ns ( 55.88 % ) " "Info: Total interconnect delay = 2.941 ns ( 55.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.263 ns" { o_data[9]~reg0 o_data[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.263 ns" { o_data[9]~reg0 {} o_data[9] {} } { 0.000ns 2.941ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { clk clk_25M o_data[9]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.588 ns" { clk {} clk~combout {} clk_25M {} o_data[9]~reg0 {} } { 0.000ns 0.000ns 1.738ns 4.475ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.263 ns" { o_data[9]~reg0 o_data[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.263 ns" { o_data[9]~reg0 {} o_data[9] {} } { 0.000ns 2.941ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}