fifo_cntl.hif

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

Version 8.0 Build 215 05/29/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
fifo_cntl
# storage
db|fifo_cntl.(0).cnf
db|fifo_cntl.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
fifo_cntl.v
ff282999704174861340771dd28c631
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
NUM
4096
PARAMETER_SIGNED_DEC
DEF
IDLE
0
PARAMETER_SIGNED_DEC
DEF
WORK
1
PARAMETER_SIGNED_DEC
DEF
CH_NUM
8
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
|
}
# macro_sequence

# end
# complete