📄 fifo_cntl.map.rpt
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Analysis & Elaboration report for fifo_cntl
Thu Sep 04 08:48:47 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Elaboration Summary
3. Analysis & Elaboration Settings
4. Parameter Settings for User Entity Instance: Top-level Entity: |fifo_cntl
5. Analysis & Elaboration Messages
6. Analysis & Elaboration Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------+
; Analysis & Elaboration Summary ;
+-------------------------------+------------------------------------------+
; Analysis & Elaboration Status ; Successful - Thu Sep 04 08:48:47 2008 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; fifo_cntl ;
; Top-level Entity Name ; fifo_cntl ;
; Family ; Cyclone II ;
+-------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Elaboration Settings ;
+--------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C8Q208C8 ; ;
; Top-level entity name ; fifo_cntl ; fifo_cntl ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+--------------------------------------------------------------+--------------------+--------------------+
+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fifo_cntl ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------------+
; NUM ; 4096 ; Signed Integer ;
; IDLE ; 0 ; Signed Integer ;
; WORK ; 1 ; Signed Integer ;
; CH_NUM ; 8 ; Signed Integer ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------+
; Analysis & Elaboration Messages ;
+---------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Elaboration
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Thu Sep 04 08:48:37 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo_cntl -c fifo_cntl --analysis_and_elaboration
Info: Found 1 design units, including 1 entities, in source file fifo_cntl.v
Info: Found entity 1: fifo_cntl
Info: Elaborating entity "fifo_cntl" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at fifo_cntl.v(39): object "btn_b" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(61): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(66): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(73): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(75): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(80): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(113): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at fifo_cntl.v(118): truncated value with size 32 to match size of target (4)
Info: Generated suppressed messages file D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.map.smsg
Info: Quartus II Analysis & Elaboration was successful. 0 errors, 8 warnings
Info: Peak virtual memory: 151 megabytes
Info: Processing ended: Thu Sep 04 08:48:48 2008
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:03
+--------------------------------------------+
; Analysis & Elaboration Suppressed Messages ;
+--------------------------------------------+
The suppressed messages can be found in D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.map.smsg.
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