fifo_cntl.sim.rpt

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

; |fifo_cntl|Add1~187        ; |fifo_cntl|Add1~187        ; combout          ;
; |fifo_cntl|Add1~187        ; |fifo_cntl|Add1~188        ; cout             ;
; |fifo_cntl|Add1~189        ; |fifo_cntl|Add1~189        ; combout          ;
; |fifo_cntl|Add1~189        ; |fifo_cntl|Add1~190        ; cout0            ;
; |fifo_cntl|Add1~191        ; |fifo_cntl|Add1~191        ; combout          ;
; |fifo_cntl|Add1~191        ; |fifo_cntl|Add1~192        ; cout0            ;
; |fifo_cntl|Add1~193        ; |fifo_cntl|Add1~193        ; combout          ;
; |fifo_cntl|Add1~193        ; |fifo_cntl|Add1~194        ; cout0            ;
; |fifo_cntl|Add1~195        ; |fifo_cntl|Add1~195        ; combout          ;
; |fifo_cntl|Add1~195        ; |fifo_cntl|Add1~196        ; cout0            ;
; |fifo_cntl|Add1~197        ; |fifo_cntl|Add1~197        ; combout          ;
; |fifo_cntl|channel[0]~416  ; |fifo_cntl|channel[0]~416  ; combout          ;
; |fifo_cntl|Add0~74         ; |fifo_cntl|Add0~74         ; combout          ;
; |fifo_cntl|Add0~74         ; |fifo_cntl|Add0~75         ; cout0            ;
; |fifo_cntl|Add0~74         ; |fifo_cntl|Add0~75COUT1    ; cout1            ;
; |fifo_cntl|Add0~76         ; |fifo_cntl|Add0~76         ; combout          ;
; |fifo_cntl|Add0~76         ; |fifo_cntl|Add0~77         ; cout0            ;
; |fifo_cntl|Add0~76         ; |fifo_cntl|Add0~77COUT1    ; cout1            ;
; |fifo_cntl|Add0~78         ; |fifo_cntl|Add0~78         ; combout          ;
; |fifo_cntl|Add0~78         ; |fifo_cntl|Add0~79         ; cout0            ;
; |fifo_cntl|Add0~78         ; |fifo_cntl|Add0~79COUT1    ; cout1            ;
; |fifo_cntl|Add0~80         ; |fifo_cntl|Add0~80         ; combout          ;
; |fifo_cntl|full            ; |fifo_cntl|full~corein     ; combout          ;
; |fifo_cntl|empty           ; |fifo_cntl|empty~corein    ; combout          ;
; |fifo_cntl|clk             ; |fifo_cntl|clk~corein      ; combout          ;
; |fifo_cntl|o_data[0]       ; |fifo_cntl|o_data[0]       ; padio            ;
; |fifo_cntl|o_data[1]       ; |fifo_cntl|o_data[1]       ; padio            ;
; |fifo_cntl|o_data[2]       ; |fifo_cntl|o_data[2]       ; padio            ;
; |fifo_cntl|o_data[3]       ; |fifo_cntl|o_data[3]       ; padio            ;
; |fifo_cntl|o_data[4]       ; |fifo_cntl|o_data[4]       ; padio            ;
; |fifo_cntl|o_data[5]       ; |fifo_cntl|o_data[5]       ; padio            ;
; |fifo_cntl|o_data[6]       ; |fifo_cntl|o_data[6]       ; padio            ;
; |fifo_cntl|o_data[7]       ; |fifo_cntl|o_data[7]       ; padio            ;
; |fifo_cntl|o_data[8]       ; |fifo_cntl|o_data[8]       ; padio            ;
; |fifo_cntl|o_data[9]       ; |fifo_cntl|o_data[9]       ; padio            ;
; |fifo_cntl|o_data[11]      ; |fifo_cntl|o_data[11]      ; padio            ;
; |fifo_cntl|o_data[12]      ; |fifo_cntl|o_data[12]      ; padio            ;
; |fifo_cntl|o_data[13]      ; |fifo_cntl|o_data[13]      ; padio            ;
; |fifo_cntl|o_data[14]      ; |fifo_cntl|o_data[14]      ; padio            ;
; |fifo_cntl|o_data[15]      ; |fifo_cntl|o_data[15]      ; padio            ;
; |fifo_cntl|slwr            ; |fifo_cntl|slwr            ; padio            ;
; |fifo_cntl|led[0]          ; |fifo_cntl|led[0]          ; padio            ;
; |fifo_cntl|led[1]          ; |fifo_cntl|led[1]          ; padio            ;
; |fifo_cntl|led[2]          ; |fifo_cntl|led[2]          ; padio            ;
; |fifo_cntl|ifclk           ; |fifo_cntl|ifclk           ; padio            ;
+----------------------------+----------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                   ;
+----------------------------+----------------------------+------------------+
; Node Name                  ; Output Port Name           ; Output Port Type ;
+----------------------------+----------------------------+------------------+
; |fifo_cntl|o_data[10]~reg0 ; |fifo_cntl|o_data[10]~reg0 ; regout           ;
; |fifo_cntl|counter[11]     ; |fifo_cntl|counter[11]     ; regout           ;
; |fifo_cntl|num[4]          ; |fifo_cntl|num[4]          ; regout           ;
; |fifo_cntl|num[3]          ; |fifo_cntl|num[3]          ; regout           ;
; |fifo_cntl|counter[10]     ; |fifo_cntl|counter[10]     ; regout           ;
; |fifo_cntl|Add1~179        ; |fifo_cntl|Add1~180        ; cout0            ;
; |fifo_cntl|Add1~181        ; |fifo_cntl|Add1~182        ; cout0            ;
; |fifo_cntl|Add1~183        ; |fifo_cntl|Add1~184        ; cout0            ;
; |fifo_cntl|Add1~185        ; |fifo_cntl|Add1~186        ; cout0            ;
; |fifo_cntl|Add1~189        ; |fifo_cntl|Add1~190COUT1   ; cout1            ;
; |fifo_cntl|Add1~191        ; |fifo_cntl|Add1~192COUT1   ; cout1            ;
; |fifo_cntl|Add1~193        ; |fifo_cntl|Add1~194COUT1   ; cout1            ;
; |fifo_cntl|Add1~195        ; |fifo_cntl|Add1~196COUT1   ; cout1            ;
; |fifo_cntl|Add1~197        ; |fifo_cntl|Add1~198        ; cout             ;
; |fifo_cntl|Add1~199        ; |fifo_cntl|Add1~199        ; combout          ;
; |fifo_cntl|Add0~72         ; |fifo_cntl|Add0~72         ; combout          ;
; |fifo_cntl|Add0~80         ; |fifo_cntl|Add0~81         ; cout0            ;
; |fifo_cntl|Add0~80         ; |fifo_cntl|Add0~81COUT1    ; cout1            ;
; |fifo_cntl|btn[0]          ; |fifo_cntl|btn[0]~corein   ; combout          ;
; |fifo_cntl|btn[1]          ; |fifo_cntl|btn[1]~corein   ; combout          ;
; |fifo_cntl|o_data[10]      ; |fifo_cntl|o_data[10]      ; padio            ;
; |fifo_cntl|fifoadr[0]      ; |fifo_cntl|fifoadr[0]      ; padio            ;
; |fifo_cntl|fifoadr[1]      ; |fifo_cntl|fifoadr[1]      ; padio            ;
; |fifo_cntl|pktend          ; |fifo_cntl|pktend          ; padio            ;
; |fifo_cntl|slcs            ; |fifo_cntl|slcs            ; padio            ;
+----------------------------+----------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                   ;
+----------------------------+----------------------------+------------------+
; Node Name                  ; Output Port Name           ; Output Port Type ;
+----------------------------+----------------------------+------------------+
; |fifo_cntl|o_data[10]~reg0 ; |fifo_cntl|o_data[10]~reg0 ; regout           ;
; |fifo_cntl|counter[9]      ; |fifo_cntl|counter[9]      ; regout           ;
; |fifo_cntl|counter[11]     ; |fifo_cntl|counter[11]     ; regout           ;
; |fifo_cntl|num[4]          ; |fifo_cntl|num[4]          ; regout           ;
; |fifo_cntl|num[3]          ; |fifo_cntl|num[3]          ; regout           ;
; |fifo_cntl|counter[10]     ; |fifo_cntl|Equal1~108      ; combout          ;
; |fifo_cntl|counter[10]     ; |fifo_cntl|counter[10]     ; regout           ;
; |fifo_cntl|btn_a           ; |fifo_cntl|btn_a           ; regout           ;
; |fifo_cntl|Add1~179        ; |fifo_cntl|Add1~180        ; cout0            ;
; |fifo_cntl|Add1~181        ; |fifo_cntl|Add1~182        ; cout0            ;
; |fifo_cntl|Add1~183        ; |fifo_cntl|Add1~184        ; cout0            ;
; |fifo_cntl|Add1~185        ; |fifo_cntl|Add1~186        ; cout0            ;
; |fifo_cntl|Add1~189        ; |fifo_cntl|Add1~190COUT1   ; cout1            ;
; |fifo_cntl|Add1~191        ; |fifo_cntl|Add1~192COUT1   ; cout1            ;
; |fifo_cntl|Add1~193        ; |fifo_cntl|Add1~194COUT1   ; cout1            ;
; |fifo_cntl|Add1~195        ; |fifo_cntl|Add1~196COUT1   ; cout1            ;
; |fifo_cntl|Add1~197        ; |fifo_cntl|Add1~198        ; cout             ;
; |fifo_cntl|Add1~199        ; |fifo_cntl|Add1~199        ; combout          ;
; |fifo_cntl|Add0~72         ; |fifo_cntl|Add0~72         ; combout          ;
; |fifo_cntl|Add0~80         ; |fifo_cntl|Add0~81         ; cout0            ;
; |fifo_cntl|Add0~80         ; |fifo_cntl|Add0~81COUT1    ; cout1            ;
; |fifo_cntl|btn[0]          ; |fifo_cntl|btn[0]~corein   ; combout          ;
; |fifo_cntl|btn[1]          ; |fifo_cntl|btn[1]~corein   ; combout          ;
; |fifo_cntl|o_data[10]      ; |fifo_cntl|o_data[10]      ; padio            ;
; |fifo_cntl|fifoadr[0]      ; |fifo_cntl|fifoadr[0]      ; padio            ;
; |fifo_cntl|fifoadr[1]      ; |fifo_cntl|fifoadr[1]      ; padio            ;
; |fifo_cntl|pktend          ; |fifo_cntl|pktend          ; padio            ;
; |fifo_cntl|slcs            ; |fifo_cntl|slcs            ; padio            ;
+----------------------------+----------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Jul 26 11:55:05 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off fifo_cntl -c fifo_cntl
Info: Using vector source file "D:/同步FIFOIN测试通过/同步自动输入CPLD/fifo_cntl.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of fifo_cntl.vwf called fifo_cntl.sim_ori.vwf has been created in the db folder
Info: Inverted registers were found during simulation
    Info: Register: |fifo_cntl|o_data[1]~reg0
    Info: Register: |fifo_cntl|o_data[3]~reg0
    Info: Register: |fifo_cntl|o_data[5]~reg0
    Info: Register: |fifo_cntl|o_data[7]~reg0
    Info: Register: |fifo_cntl|o_data[9]~reg0
    Info: Register: |fifo_cntl|o_data[11]~reg0
    Info: Register: |fifo_cntl|o_data[13]~reg0
    Info: Register: |fifo_cntl|o_data[15]~reg0
    Info: Register: |fifo_cntl|slwr~reg0
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      76.86 %
Info: Number of transitions in simulation is 720992
Info: Vector file fifo_cntl.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 102 megabytes of memory during processing
    Info: Processing ended: Sat Jul 26 11:55:25 2008
    Info: Elapsed time: 00:00:20